Abstract: A device for interleaving/deinterleaving digital data delivered by processing elements (P0 . . . Pn-1) suitable for being used both with turbo-codes and with LDPC codes. The device includes memory banks (B0 . . . Bm-1) for storing data coming from or going to the processing elements, an interconnection network (INT) for directing the data between the processing elements and the memory banks, and a control unit (CTRL) for controlling the interconnection network and the memory banks. The control unit (CTRL) includes a calculation circuit (CAL) capable of the online generation of command words for the interconnection network and addressing and control sequences of the memory banks, ensuring conflict-free memory access on the basis of the interleaving rule to be applied, the size of the digital data frames, the number of processing units and memory banks, and the interconnection network.

Abstract: A method of producing data representing an identifier of a neuron from a cluster of L neurons belonging to a neural network having C clusters. L and C are natural integers of values greater than or equal to two. Each neuron has at least two states. The method includes, for at least one current cluster Ci: producing a set E of neural states originating from at least one cluster Cj, j?i; producing a set A of coefficients of adjacency between at least one neuron of the current cluster Ci, and at least one neuron of a cluster Cj of the neural network j?i; calculating, as a function of the set E of neural states, the set A of adjacency coefficients and, as a function of state(s) of the neurons of the current cluster Ci, at least one winning neuron NG.

Abstract: A device for interleaving/deinterleaving digital data delivered by processing elements (P0 . . . Pn-1) suitable for being used both with turbo-codes and with LDPC codes. The device includes memory banks (B0 . . . Bm-1) for storing data coming from or going to the processing elements, an interconnection network (INT) for directing the data between the processing elements and the memory banks, and a control unit (CTRL) for controlling the interconnection network and the memory banks. The control unit (CTRL) includes a calculation circuit (CAL) capable of the online generation of command words for the interconnection network and addressing and control sequences of the memory banks, ensuring conflict-free memory access on the basis of the interleaving rule to be applied, the size of the digital data frames, the number of processing units and memory banks, and the interconnection network.

Abstract: A data interleaving device is provided that includes an input, an output, and a data interleaver coupled to the input and the output. The input receives data originating from a plurality of processing blocks. The output transfers interleaved data to the plurality of processing blocks. The data interleaver includes a controller, at least one interconnection module, and a plurality of memories. The controller prepares a data-to-memory assignment data structure. The at least one interconnection module switches data in parallel according to the data-to-memory assignment data structure and acts identically on all data switched simultaneously in parallel. The plurality of memories store the switched data. The data interleaver interleaves data received from the input and provides the interleaved data at the output.

Abstract: A data interleaving device is provided that includes an input, an output, and a data interleaver coupled to the input and the output. The input receives data originating from a plurality of processing blocks. The output transfers interleaved data to the plurality of processing blocks. The data interleaver includes a controller, at least one interconnection module, and a plurality of memories. The controller prepares a data-to-memory assignment data structure. The at least one interconnection module switches data in parallel according to the data-to-memory assignment data structure and acts identically on all data switched simultaneously in parallel. The plurality of memories store the switched data. The data interleaver interleaves data received from the input and provides the interleaved data at the output.