Patents by Inventor Philippe Deval
Philippe Deval has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10969809Abstract: A low dropout (LDO) includes voltage inputs to receive input from voltage sources. The LDO voltage regulator includes a regulated voltage output, blocking diodes, and circuitry configured to block leakage from a first voltage input with a first blocking diode when the first voltage input is less than the regulated voltage output, and to provide the regulated voltage output from the first voltage input and a second voltage input.Type: GrantFiled: July 31, 2019Date of Patent: April 6, 2021Assignee: Microchip Technology IncorporatedInventor: Philippe Deval
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Patent number: 10852329Abstract: A current sensing circuit includes a current sense amplifier and a correction circuit. The current sense amplifier has an offset voltage. The correction circuit is configured to evaluate the offset voltage of the current sense amplifier. The correction circuit is further configured to issue a correction signal to the current sense amplifier based upon the evaluated offset voltage. The correction signal is to adjust the offset voltage.Type: GrantFiled: October 19, 2018Date of Patent: December 1, 2020Assignee: MICROCHIP TECHNOLOGY INCORPORATEDInventors: Marija Fernandez, Philippe Deval
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Patent number: 10753964Abstract: An integrated circuit device for controlling and sensing electrical current is provided. The integrated circuit device comprises a main transistor device, configured for controlling a main current, and a plurality of sensing transistor devices, configured for controlling a combined sensing current. The main transistor device and the plurality of sensing transistor devices are connected to a common gate node. The on-state resistance of the main transistor device is lower than a combined on-state resistance of the plurality of sensing transistor devices. The sensing transistor devices are distributed throughout at least a section of the integrated circuit to reduce an influence of at least one local property of the integrated circuit device on the combined sensing current.Type: GrantFiled: April 24, 2018Date of Patent: August 25, 2020Assignee: MICROCHIP TECHNOLOGY INCORPORATEDInventors: Greg Dix, Philippe Deval
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Publication number: 20200042028Abstract: A low dropout (LDO) includes voltage inputs to receive input from voltage sources. The LDO voltage regulator includes a regulated voltage output, blocking diodes, and circuitry configured to block leakage from a first voltage input with a first blocking diode when the first voltage input is less than the regulated voltage output, and to provide the regulated voltage output from the first voltage input and a second voltage input.Type: ApplicationFiled: July 31, 2019Publication date: February 6, 2020Applicant: Microchip Technology IncorporatedInventor: Philippe Deval
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Publication number: 20190128932Abstract: A current sensing circuit includes a current sense amplifier and a correction circuit. The current sense amplifier has an offset voltage. The correction circuit is configured to evaluate the offset voltage of the current sense amplifier. The correction circuit is further configured to issue a correction signal to the current sense amplifier based upon the evaluated offset voltage. The correction signal is to adjust the offset voltage.Type: ApplicationFiled: October 19, 2018Publication date: May 2, 2019Applicant: Microchip Technology IncorporatedInventors: Marija Fernandez, Philippe Deval
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Publication number: 20180313874Abstract: An integrated circuit device for controlling and sensing electrical current is provided. The integrated circuit device comprises a main transistor device, configured for controlling a main current, and a plurality of sensing transistor devices, configured for controlling a combined sensing current. The main transistor device and the plurality of sensing transistor devices are connected to a common gate node. The on-state resistance of the main transistor device is lower than a combined on-state resistance of the plurality of sensing transistor devices. The sensing transistor devices are distributed throughout at least a section of the integrated circuit to reduce an influence of at least one local property of the integrated circuit device on the combined sensing current.Type: ApplicationFiled: April 24, 2018Publication date: November 1, 2018Applicant: Microchip Technology IncorporatedInventors: Greg Dix, Philippe Deval
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Patent number: 9735820Abstract: A LIN receiver includes a single, low power structure for both sleep and silent modes, with a single comparator for detecting LIN signaling during both sleep and silent modes as well as during active mode. In some embodiments, full receiving capability is implemented with a current as low as 5 microamps. In particular, dominant and recessive levels for the wakeup bloc are identical to those of standard LIN levels, fixed at about 3.5 V. Consequently, full LIN receiving capability is available during sleep mode.Type: GrantFiled: March 15, 2013Date of Patent: August 15, 2017Assignee: MICROCHIP TECHNOLOGY INCORPORATEDInventors: Philippe Deval, Marija Fernandez, Patrick Besseux
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Patent number: 9607978Abstract: A double-diffused metal oxide semiconductor (DMOS) structure is configured as an open drain output driver having electrostatic discharge (ESD) protection and a reverse voltage blocking diode inherent in the structure and without requiring metal connections for the ESD and reverse voltage blocking diode protections.Type: GrantFiled: January 29, 2014Date of Patent: March 28, 2017Assignee: MICROCHIP TECHNOLOGY INCORPORATEDInventors: Philippe Deval, Marija Fernandez, Patrick Besseux, Rohan Braithwaite
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Patent number: 9509321Abstract: A clock oscillator includes a high speed oscillator generating a high speed clock signal and comprising a digital trimming function; a counter receiving said high speed clock signal at a clock input; a time base having a low drift and controlling said counter, wherein the counter generates a difference between a reference value and a counter value; and a digital integrator receiving said difference value and providing trimming data for said high speed oscillator.Type: GrantFiled: November 26, 2014Date of Patent: November 29, 2016Assignee: MICROCHIP TECHNOLOGY INCORPORATEDInventors: Philippe Deval, Gabriele Bellini, Patrick Besseux, Francesco Mazzilli
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Publication number: 20150146832Abstract: A clock oscillator includes a high speed oscillator generating a high speed clock signal and comprising a digital trimming function; a counter receiving said high speed clock signal at a clock input; a time base having a low drift and controlling said counter, wherein the counter generates a difference between a reference value and a counter value; and a digital integrator receiving said difference value and providing trimming data for said high speed oscillator.Type: ApplicationFiled: November 26, 2014Publication date: May 28, 2015Inventors: Philippe Deval, Gabriele Bellini, Patrick Besseux, Francesco Mazzilli
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Publication number: 20140269996Abstract: A LIN receiver includes a single, low power structure for both sleep and silent modes, with a single comparator for detecting LIN signaling during both sleep and silent modes as well as during active mode. In some embodiments, full receiving capability is implemented with a current as low as 5 microamps. In particular, dominant and recessive levels for the wakeup bloc are identical to those of standard LIN levels, fixed at about 3.5 V. Consequently, full LIN receiving capability is available during sleep mode.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: MICROCHIP TECHNOLOGY INCORPORATEDInventors: Philippe Deval, Marija Fernandez, Patrick Besseux
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Publication number: 20140210007Abstract: A double-diffused metal oxide semiconductor (DMOS) structure is configured as an open drain output driver having electrostatic discharge (ESD) protection and a reverse voltage blocking diode inherent in the structure and without requiring metal connections for the ESD and reverse voltage blocking diode protections.Type: ApplicationFiled: January 29, 2014Publication date: July 31, 2014Inventors: Philippe Deval, Marija Fernandez, Patrick Besseux, Rohan Braithwaite
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Patent number: 8786266Abstract: A high voltage switching regulator has significantly reduced current sensing delay between measurement of input current and generation of sensed current values, while maintaining good accuracy of the current through a power transistor using current replication and a current conveyor. High sensing accuracy of the input current ensures good load regulation, and low sensing delay ensures fixed duty cycle over a wide range of output currents and high input to output voltage ratios. A current conveyor is used to transfer high side current values to low side control circuits, e.g., pulse width modulation (PWM) control. The current conveyor is always on, e.g., some current flow is always present, thus minimizing any current measurement delay. This is accomplished by dynamically biasing the current conveyor by draining to ground a current equal to the sensed current. Wherein balancing of the current conveyor is ensured and offset at the input of the current conveyor is minimized.Type: GrantFiled: January 6, 2011Date of Patent: July 22, 2014Assignee: Microchip Technology IncorporatedInventors: Philippe Deval, Philippe Gimmel, Marius Budaes, Daniel Leonescu, Terry Cleveland, Scott Dearborn
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Patent number: 8735979Abstract: Mutual triggering of electrostatic discharge (ESD) fingers is improved by creating a base contact in each individual finger and connecting all of these base contacts in parallel. The local base contact in each ESD finger is located at a position where the base voltage significantly increases when the ESD current increases. Thus when an ESD finger is triggered its local base voltage will tend to significantly increase. Since all of the ESD finger bases are connected in parallel this local voltage increase will forward bias the base-emitter junctions of the other ESD fingers, thus triggering them all. By sharing the triggering current from the fastest ESD finger with the slower ones ensures that all ESD fingers are triggered during an ESD event.Type: GrantFiled: July 19, 2012Date of Patent: May 27, 2014Assignee: Microchip Technology IncorporatedInventors: Philippe Deval, Marija Fernandez, Patrick Besseux
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Patent number: 8599053Abstract: A gain amplifier may have a differential amplifier with feedback capacitors; a switched input stage having first and second outputs coupled with the differential amplifier, and having: first and second capacitors, a first input receiving a first signal of a differential input signal; a second input receiving a second signal of the differential input signal; a first plurality of switches controlled by a first clock signal to connect the first terminals of the first capacitor with the first or second input, respectively and to connect the first terminals of the second capacitors with the second and first input, respectively; and a second plurality of switches controlled by a phase shifted clock signal to connect the second terminal of the first capacitor with a first or second input of the differential amplifier and connecting the second terminal of the second capacitor with the second or first input of the differential amplifier.Type: GrantFiled: December 14, 2011Date of Patent: December 3, 2013Assignee: Microchip Technology IncorporatedInventors: Vincent Quiquempoix, Philippe Deval, Fabien Vaucher
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Patent number: 8462473Abstract: For adaptive electrostatic discharge (ESD) protection, an integrated circuit device having an adaptive electrostatic discharge (ESD) protection, has an external connection pin to be protected from ESD; an external ground connection pin; an adaptive electrostatic discharge (ESD) protection circuit having: an ESD protection N-metal oxide semiconductor (NMOS) transistor having drain connected to the external connection pin and a source and bulk connected to ground; a resistor coupled between a gate of the NMOS transistor and ground; a first PMOS transistor having a source coupled to a gate of the NMOS transistor and a drain connected to ground; a first capacitor having a first terminal connected to the external connection pin and a second terminal that is coupled with the gate of the NMOS transistor, wherein the first capacitor within the adaptive ESD protection circuit is the only capacitor connected to the external connection pin.Type: GrantFiled: November 3, 2011Date of Patent: June 11, 2013Assignee: Microchip Technology IncorporatedInventors: Philippe Deval, Nicolas Furrer, Bart De Geeter
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Publication number: 20130020646Abstract: Mutual triggering of electrostatic discharge (ESD) fingers is improved by creating a base contact in each individual finger and connecting all of these base contacts in parallel. The local base contact in each ESD finger is located at a position where the base voltage significantly increases when the ESD current increases. Thus when an ESD finger is triggered its local base voltage will tend to significantly increase. Since all of the ESD finger bases are connected in parallel this local voltage increase will forward bias the base-emitter junctions of the other ESD fingers, thus triggering them all. By sharing the triggering current from the fastest ESD finger with the slower ones ensures that all ESD fingers are triggered during an ESD event.Type: ApplicationFiled: July 19, 2012Publication date: January 24, 2013Inventors: Philippe Deval, Marija Fernandez, Patrick Besseux
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Patent number: 8223053Abstract: A sigma-delta modulator may have a plurality of capacitor pairs, a plurality of switches to couple any pair of capacitors from the plurality of capacitor pairs selectively to an input signal or a reference signal, and a control unit operable to control sampling through the switches to perform a charge transfer in two phases wherein any pair of capacitors can be selected to be assigned to the input signal or the reference signal, and wherein after a plurality of charge transfers a gain error cancellation is performed by rotating the capacitor pairs cyclically such that after a rotation cycle, each capacitor pair has been assigned a first predetermined number of times to the input signal, and has also been assigned a second predetermined number of times to the reference signal.Type: GrantFiled: July 8, 2010Date of Patent: July 17, 2012Assignee: Microchip Technology IncorporatedInventors: Philippe Deval, Vincent Quiquempoix
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Publication number: 20120161994Abstract: A gain amplifier may have a differential amplifier with feedback capacitors; a switched input stage having first and second outputs coupled with the differential amplifier, and having: first and second capacitors, a first input receiving a first signal of a differential input signal; a second input receiving a second signal of the differential input signal; a first plurality of switches controlled by a first clock signal to connect the first terminals of the first capacitor with the first or second input, respectively and to connect the first terminals of the second capacitors with the second and first input, respectively; and a second plurality of switches controlled by a phase shifted clock signal to connect the second terminal of the first capacitor with a first or second input of the differential amplifier and connecting the second terminal of the second capacitor with the second or first input of the differential amplifier.Type: ApplicationFiled: December 14, 2011Publication date: June 28, 2012Inventors: Vincent Quiquempoix, Philippe Deval, Fabien Vaucher
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Publication number: 20120154963Abstract: For adaptive electrostatic discharge (ESD) protection, an integrated circuit device having an adaptive electrostatic discharge (ESD) protection, has an external connection pin to be protected from ESD; an external ground connection pin; an adaptive electrostatic discharge (ESD) protection circuit having: an ESD protection N-metal oxide semiconductor (NMOS) transistor having drain connected to the external connection pin and a source and bulk connected to ground; a resistor coupled between a gate of the NMOS transistor and ground; a first PMOS transistor having a source coupled to a gate of the NMOS transistor and a drain connected to ground; a first capacitor having a first terminal connected to the external connection pin and a second terminal that is coupled with the gate of the NMOS transistor, wherein the first capacitor within the adaptive ESD protection circuit is the only capacitor connected to the external connection pin.Type: ApplicationFiled: November 3, 2011Publication date: June 21, 2012Inventors: Philippe Deval, Nicolas Furrer, Bart De Geeter