Patents by Inventor Philippe Givelin
Philippe Givelin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9722419Abstract: An electrostatic discharge protection circuit comprises at least two electrostatic discharge protection units connected in series between respective pairs of at least three input terminals, one of the input terminals being a reference input terminal. Each of the units comprises a silicon controlled rectifier and a current mirror. The output of the silicon controlled rectifier constitutes a first output of the respective unit and is connected to an input terminal of the circuit. The output of the current mirror constitutes a second output of the respective unit and is connected with the reference input terminal of the circuit. Thus the units are connected in series but the output terminals of the current mirrors are all connected with the reference input terminal, which may be a ground terminal, so as to minimize the breakdown resistance of the circuit.Type: GrantFiled: May 4, 2015Date of Patent: August 1, 2017Assignee: NXP USA, Inc.Inventors: Patrice Besse, Philippe Givelin, Jean Philippe Laine
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Patent number: 9651968Abstract: The present invention pertains to a linear power regulator device that includes an internal pass device, a driver device having a driver output arranged to drive the internal pass device via the driver output. The linear power regulator device also includes an external connection connectable or connected to an external pass device; and the driver device is arranged to drive the external pass device via the driver output and the external connection.Type: GrantFiled: July 19, 2012Date of Patent: May 16, 2017Assignee: NXP USA, Inc.Inventors: Alexandre Pujol, Philippe Givelin, Mohammed Mansri
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Patent number: 9638744Abstract: An integrated circuit device comprises a first integrated circuit and a second integrated circuit wherein the first and second integrated circuits are comprised on a single semiconductor die. The second integrated circuit is a safety circuit arranged to monitor the operation of the first integrated circuit, report any detected faults and drive the device into a failsafe state if a fault is detected. The first integrated circuit may be a power management module for a safety critical system. An isolation barrier in the form of a trench is formed between the two integrated circuits so that the safety circuit is protected from any high voltage or thermal stresses arising in the first integrated circuit. The device has particular application to automotive safety-critical systems such as electric power steering systems.Type: GrantFiled: July 2, 2012Date of Patent: May 2, 2017Assignee: NXP USA, Inc.Inventors: Valérie Bernon-Enjalbert, Guillaume Founaud, Yuan Gao, Philippe Givelin
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Patent number: 9620992Abstract: A power safety circuit comprises a power sense terminal; an output terminal; an output driver unit connected to the output terminal; an input terminal connectable to receive a first power from a power source and arranged to supply the first power to the output driver unit; and a power detection unit arranged to detect a state of the input terminal and provide a power sense signal to the power sense terminal; wherein the power sense terminal is arranged to supply a second power to the output driver unit when the power sense signal indicates a level of the first power below a minimum level for driving the output terminal. An integrated circuit device comprises at least one power safety circuit. A safety critical system comprises at least one integrated circuit device with at least one power safety circuit.Type: GrantFiled: October 27, 2011Date of Patent: April 11, 2017Assignee: NXP USA, Inc.Inventors: Philippe Givelin, Valerie Bernon-Enjalbert, Guillaume Founaud
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Patent number: 9606159Abstract: An electronic device for generating an error signal in response to an electrostatic discharge perturbation is described. The device may comprise: a detection unit for generating a detection signal in response to said electrostatic discharge perturbation, said detection signal correlating in time with said electrostatic discharge perturbation; a clock for generating a clock signal having a clock period; and a protection unit for generating an error signal in response to said detection signal only when a duration of said detection signal exceeds a predefined multiple of said clock period. A method of generating an error signal in response to an electrostatic discharge perturbation, for protecting electronic circuitry, is also disclosed.Type: GrantFiled: April 26, 2012Date of Patent: March 28, 2017Assignee: NXP USA, Inc.Inventors: Patrice Besse, Valérie Bernon-Enjalbert, Philippe Givelin
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Publication number: 20160156180Abstract: An electrostatic discharge protection circuit comprises at least two electrostatic discharge protection units connected in series between respective pairs of at least three input terminals, one of the input terminals being a reference input terminal. Each of the units comprises a silicon controlled rectifier and a current mirror. The output of the silicon controlled rectifier constitutes a first output of the respective unit and is connected to an input terminal of the circuit. The output of the current mirror constitutes a second output of the respective unit and is connected with the reference input terminal of the circuit. Thus the units are connected in series but the output terminals of the current mirrors are all connected with the reference input terminal, which may be a ground terminal, so as to minimise the breakdown resistance of the circuit.Type: ApplicationFiled: May 4, 2015Publication date: June 2, 2016Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: PATRICE BESSE, PHILIPPE GIVELIN, JEAN PHILIPPE LAINE
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Patent number: 9318448Abstract: A packaged semiconductor device comprising a package and a semiconductor device is described. The semiconductor device comprises a first and a second GND-pad bonded to one or more GND-pins with a first and a second bond wire respectively, a first functional pad bonded to a first functional pin with a third bond wire, a semiconductor layer of a P-type conductivity, a first semiconductor component and a second semiconductor component. The first semiconductor component is arranged to, when a transient current is applied to the first functional pin, divert at least part of the transient current to the first GND-pad from the first P-region to the first GND-pad via at least a first PN-junction. The second semiconductor component comprises a second N-type region of a terminal of the second semiconductor component associated with the first functional pad. The first GND-pad is in contact with a second P-type region. The second GND-pad is in contact with a third N-type region.Type: GrantFiled: May 30, 2012Date of Patent: April 19, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Patrice Besse, Kamel Abouda, Valerie Bernon-Enjalbert, Philippe Givelin
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Publication number: 20150331040Abstract: An integrated circuit device comprises a first integrated circuit and a second integrated circuit wherein the first and second integrated circuits are comprised on a single semiconductor die. The second integrated circuit is a safety circuit arranged to monitor the operation of the first integrated circuit, report any detected faults and drive the device into a failsafe state if a fault is detected. The first integrated circuit may be a power management module for a safety critical system. An isolation barrier in the form of a trench is formed between the two integrated circuits so that the safety circuit is protected from any high voltage or thermal stresses arising in the first integrated circuit. The device has particular application to automotive safety-critical systems such as electric power steering systems.Type: ApplicationFiled: July 2, 2012Publication date: November 19, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Valérie BERNON-ENJALBERT, Guillaume FOUNAUD, Yuan GAO, Philippe GIVELIN
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Patent number: 9099306Abstract: An integrated circuit (IC) device including an electrostatic discharge (ESD) protection network for a high voltage application. The ESD protection network includes a common diode structure coupled between an external contact of the IC device and a substrate of the IC device, such that the common diode structure is forward biased towards the external contact, a Darlington transistor structure coupled between the external contact and the substrate of the IC device, and the Darlington transistor structure includes: an emitter node coupled to the external contact; a collector node coupled to the substrate; and a base node coupled between the emitter node of the Darlington transistor structure and the common diode structure. The at least one ESD protection network further comprises an isolation diode structure coupled between the emitter node and the base node of the Darlington transistor structure such that the isolation diode structure is forward biased towards the base node.Type: GrantFiled: January 20, 2012Date of Patent: August 4, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Patrice Besse, Philippe Givelin, Eric Rolland
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Publication number: 20150212531Abstract: The present invention pertains to a linear power regulator device that includes an internal pass device, a driver device having a driver output arranged to drive the internal pass device via the driver output. The linear power regulator device also includes an external connection connectable or connected to an external pass device; and the driver device is arranged to drive the external pass device via the driver output and the external connection.Type: ApplicationFiled: July 19, 2012Publication date: July 30, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Alexandre Pujol, Philippe Givelin, Mohammed Mansri
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Patent number: 9077171Abstract: A reference voltage loss monitoring circuit having a first and second reference node. The reference nodes are connected to a voltage reference. A first connection device is connects the first reference node to the second reference node, and includes a first diode to allow a current flowing from the first reference node to the reference ground node and not conversely. The first diode includes a first main transistor. A second connection device connects the second reference node to the first reference node, and includes a second diode to allow a current flowing from the second reference node to first reference node and not conversely. The second diode includes a second main transistor. Each of the first and second connection devices further includes a secondary transistor mirrored with the main transistor of the connection devices.Type: GrantFiled: May 27, 2011Date of Patent: July 7, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Philippe Givelin, Patrice Besse, Estelle Huynh
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Publication number: 20150129928Abstract: A packaged semiconductor device comprising a package and a semiconductor device is described. The semiconductor device comprises a first and a second GND-pad bonded to one or more GND-pins with a first and a second bond wire respectively, a first functional pad bonded to a first functional pin with a third bond wire, a semiconductor layer of a P-type conductivity, a first semiconductor component and a second semiconductor component. The first semiconductor component is arranged to, when a transient current is applied to the first functional pin, divert at least part of the transient current to the first GND-pad from the first P-region to the first GND-pad via at least a first PN-junction. The second semiconductor component comprises a second N-type region of a terminal of the second semiconductor component associated with the first functional pad. The first GND-pad is in contact with a second P-type region. The second GND-pad is in contact with a third N-type region.Type: ApplicationFiled: May 30, 2012Publication date: May 14, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Patrice Besse, Kamel Abouda, Valerie Bernon-Enjalbert, Philippe Givelin
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Publication number: 20150076556Abstract: An integrated circuit (IC) device including an electrostatic discharge (ESD) protection network for a high voltage application. The ESD protection network includes a common diode structure coupled between an external contact of the IC device and a substrate of the IC device, such that the common diode structure is forward biased towards the external contact, a Darlington transistor structure coupled between the external contact and the substrate of the IC device, and the Darlington transistor structure includes: an emitter node coupled to the external contact; a collector node coupled to the substrate; and a base node coupled between the emitter node of the Darlington transistor structure and the common diode structure. The at least one ESD protection network further comprises an isolation diode structure coupled between the emitter node and the base node of the Darlington transistor structure such that the isolation diode structure is forward biased towards the base node.Type: ApplicationFiled: January 20, 2012Publication date: March 19, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Patrice Besse, Philippe Givelin, Eric Rolland
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Publication number: 20150061728Abstract: An electronic device for generating an error signal in response to an electrostatic discharge perturbation is described. The device may comprise: a detection unit for generating a detection signal in response to said electrostatic discharge perturbation, said detection signal correlating in time with said electrostatic discharge perturbation; a clock for generating a clock signal having a clock period; and a protection unit for generating an error signal in response to said detection signal only when a duration of said detection signal exceeds a predefined multiple of said clock period. A method of generating an error signal in response to an electrostatic discharge perturbation, for protecting electronic circuitry, is also disclosed.Type: ApplicationFiled: April 26, 2012Publication date: March 5, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Patrice Besse, Valérie Bernon-Enjalbert, Philippe Givelin
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Publication number: 20140300193Abstract: A power safety circuit comprises a power sense terminal; an output terminal; an output driver unit connected to the output terminal; an input terminal connectable to receive a first power from a power source and arranged to supply the first power to the output driver unit; and a power detection unit arranged to detect a state of the input terminal and provide a power sense signal to the power sense terminal; wherein the power sense terminal is arranged to supply a second power to the output driver unit when the power sense signal indicates a level of the first power below a minimum level for driving the output terminal. An integrated circuit device comprises at least one power safety circuit. A safety critical system comprises at least one integrated circuit device with at least one power safety circuit.Type: ApplicationFiled: October 27, 2011Publication date: October 9, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Philippe Givelin, Valerie Bernon-Enjalbert, Guillaume Founaud