Abstract: A communication device includes at least one receiver and at least one transmitter. The communication device also includes a cryptographic processor coupled to at least one of the at least one receiver and the at least one transmitter. The communication device further includes the cryptographic processor enabling high speed cryptographic modes. The cryptographic processor includes a resource virtualization subsystem having an address offset register bank and an offset adder coupled to a microaddress calculation logic on a bank virtualization subsystem.

Abstract: The present invention is a rotating priority queue manager. A rotating priority queue manager in accordance with the present invention may include a plurality of source data channels, a corresponding plurality of processing resources, and an arbitrating interface directing the flow of data from the source channels to the processing resources where the data must flow over a shared data path. The plurality of processing resources may comprise any system of parallel processors where the servicing of input data must be carried out in a manner where there the maximum latency for processing a given data channel is determinable, the arbitration between channels is equal, no input channel may prevent another channel from being serviced, and lower priority processing resources are not prohibited from receiving input data if higher priority processing resources are not currently available or if higher priority data is not currently available.