Abstract: A generator of phases of a detector integrates at least one elementary machine for interpreting a microcode stored in a register. Each elementary machine includes at least one control input having a logic level change detector. Each elementary machine also includes at least one phase output having a controlled switch, enabling to define the logic level of the phase output, and a controlled inverter enabling to toggle the logic level of the phase output. Further, each elementary machine includes at least one clock signal associated with a counter, and a unit for loading the instructions and the arguments stored in the register, the instructions being coded over 3 bits.

Abstract: A generator of phases of a detector integrates at least one elementary machine for interpreting a microcode stored in a register. Each elementary machine includes at least one control input having a logic level change detector. Each elementary machine also includes at least one phase output having a controlled switch, enabling to define the logic level of the phase output, and a controlled inverter enabling to toggle the logic level of the phase output. Further, each elementary machine includes at least one clock signal associated with a counter, and a unit for loading the instructions and the arguments stored in the register, the instructions being coded over 3 bits.

Abstract: A circuit and a method for decoding data coded by blocks by a turbo-code including successive steps. One of the steps may use n first processors adapted to operating in parallel on n lines, or columns, of a block. Different steps may be performed in parallel on the same block of turbocoded data.

Abstract: Interleaved type processing includes a preprocessing phase in which for each initial symbol received an auxiliary symbol that includes N auxiliary complex samples is formulated, and a processing phase that includes for each auxiliary symbol an inverse Fourier transform calculation of size N. The processing phase includes elementary processing of the butterfly type corresponding to several stages of a general butterfly-like calculation graph. The various stages of the graph are implemented within a pipelined architecture. Upon receiving an initial symbol, two separate random access memories are simultaneously used to respectively store in a first memory the auxiliary symbol corresponding to this initial symbol, and to perform on the basis of the content of the second memory the elementary processing corresponding to a first stage of the graph. The two memories are swapped with each new receipt of an initial symbol.

Abstract: The post-processing of the transformation processing of an interleaved type is temporally nested with regards to two successive symbols, and includes storage in two separately addressable memories of identical size. The addressing of the two memories is performed successively and alternately in the natural and reverse order at the frequency with the symbol clock signal.

Abstract: A circuit and a method for decoding data coded by blocks by a turbo-code including successive steps implementing different algorithms. At least two of the successive steps are capable of being applied in parallel to different data blocks.