Abstract: A method and apparatus are described for expanding the capability of an instruction prefetch buffer. The method and apparatus enables the instruction prefetch buffer to distinguish between old prefetches that occurred before a branch in an instruction stream and new prefetches which occurred after the branch in the instruction stream. A control tag is generated each time a request for an instruction is sent to a storage. The returning instruction has appended thereto the original control tag which is then compared to the current value of control tag in the instruction prefetch buffer. If the two values match, then this is an indication that a branch has not occurred and the instruction is still required. However, if the two values of the control tag are not equal, then this is an indication that a branch in the instruction stream has occurred and that the instruction being sent from storage to the buffer is no longer required.

Abstract: A method for processing address translation exceptions occurring in a virtual memory system employing demand paging and having a plurality of registers and a real storage area, includes the steps of: (a) temporarily storing for each storage operation; (i) the effective storage address for the operation; (ii) exception control word information relative to the ones of the registers involved in the operation and the length and type of the operation; and (iii) any data to be stored during the operation; (b) retrieving the temporarily stored information to form an exception status block if an exception is generated indicating a failed operation; and (c) reinitiating the failed operation based on the information contained in the exception status block.

Abstract: Apparatus is provided for testing a data processing system which includes a microprocessor, the testing occurring with the microprocessor in place in the system. The apparatus comprises: a support microprocessor for controlling the testing, a serial-to-parallel and parallel-to-serial converter connected between the support microprocessor and the system microprocessor, means for supplying a series of level sensitive scan design (LSSD) test signals from the support microprocessor through the converter to the system microprocessor, and means for returning the results of the level sensitive scan design test signals from the system microprocessor through the converter to the support microprocessor.

Abstract: A method and apparatus expands the capability of an instruction prefetch buffer. The method and apparatus enables the instruction prefetch buffer to distinguish between old prefetches that occurred before a branch in an instruction stream and new prefetches which occurred after the branch in the instruction stream. A control tag is generated each time a request for an instruction is sent to a storage. The returning instruction has appended thereto the original control tag which is then compared to the current value of control tag in the instruction prefetch buffer. If the two values match, then this is an indication that a branch has not occurred and the instruction is still required. However, if the two values of the control tag are not equal, then this is an indication that a branch in the instruction stream has occurred and that the instruction being sent from storage to the buffer is no longer required.

Abstract: A virtual memory address translation mechanism is provided for converting virtual memory addresses provided by a CPU into real memory addresses within page frames in a large hierachial memory wherein the real memory space is substantially smaller than the scope of the virtual memory. The conversion or translation mechanism includes a combined table in the memory which includes a first list covering the respective virtual address of each memory address (Inverted Page Table or IPT) and a second list connecting each of a plurality of hashed addresses with a predetermined initial virtual address of a linked group of virtual addresses, each of which when hashed produces the connected hashed address (Hashed Addressed Table, HAT). The system also has means for hashing a selected virtual address to produce a hashed address.

Abstract: The present invention is directed to a conventional data processing system having a CPU and at least one external unit such as the main storage unit acquiring data from or providing data to the CPU and I/O bus for the transfer of data between the CPU and the external unit. The apparatus of the present invention provides for transfers to and from this external unit, e.g., main storage being overlapped with a register to register data transfer routinely carried out in the CPU to implement various CPU operations and computation functions. The CPU includes apparatus for transferring data to or from said external unit over the I/O bus during synchronized time cycles. The CPU also includes local storage apparatus which comprise a plurality of registers as well as expedients for transferring data from register to register. Control apparatus controls the register to register data transfer so that such transfers are conducted during time cycles coincident with the transfer of data to or from the external storage unit.

Abstract: The present invention is directed to a conventional data processing system having a CPU and at least one external unit such as the main storage unit acquiring data from or providing data to the CPU and I/O bus for the transfer of data between the CPU and the external unit. The apparatus of the present invention provides for transfers to and from this external unit, e.g., main storage being overlapped with a register to register data transfer routinely carried out in the CPU to implement various CPU operations and computation functions. The CPU includes apparatus for transferring data to or from said external unit over the I/O bus during synchronized time cycles. The CPU also includes local storage apparatus which comprise a plurality of registers as well as expedients for transferring data from register to register. Control apparatus controls the register to register data transfer so that such transfers are conducted during time cycles coincident with the transfer of data to or from the external storage unit.