Abstract: Techniques for storing and translating digital images of different native formats in a way that makes it unnecessary for independent manufactures of imaging devices such as digital cameras to agree on factors related to production/capture and processing of the images. Image data in a native format and an associated method are combined as part of an image object, within the meaning of classical object-oriented technology, and transferred to the host system. An abstract machine, such as a virtual machine, in the host system acts as a virtual image processor and executes the method to obtain image data in a common format. The method in each image object operates on its corresponding image data to yield an image in a common format.

Abstract: Under an embodiment, a system includes an array of analog photocells; a first plurality of shift cells, each shift cell in the first plurality of shift cells being coupled to a corresponding analog photocell; and a second plurality of shift cells, each shift cell in the second plurality of shift cells being coupled to a corresponding shift cell in the first plurality of shift cells; and a differential operational amplifier having a first input coupled to a terminating output of the first plurality of shift cells and a second input coupled to a terminating output of the second plurality of shift cells.

Abstract: Under an embodiment, a system includes an array of digital photocells; a plurality of digital holding registers, an output of each digital photocell being coupled to a corresponding digital holding register; and a plurality of subtraction units, a first input of each subtraction unit being coupled to a digital photocell and a second input of each subtraction unit being coupled to the corresponding digital holding register for the digital photocell that is coupled to the first input.

Abstract: A memory including a plurality of memory word lines and a sequential addressing circuit is provided. The sequential addressing circuit comprises at least one sequential shift register including at least one logic gate and at least one word flag cell for each of the word lines. Enablement of each memory word line depends upon the state of the word flag cell. An enable or access bit is shifted sequentially through the sequential. addressing circuit to select each of the word lines. The enable or access bit selectively bypasses or skips a word line depending on the state of its corresponding word flag cell. A method for accessing a nonvolatile writeable memory is also described. The method comprises determining at least one non-operational or defective memory bit cell of a nonvolatile writeable memory. At least one word line of the nonvolatile writeable memory is masked out, wherein the at least one word line is coupled to the at least one non-operational operational memory bit cell.

Abstract: In a computer system having a processor, a system memory, a flash memory, and a memory controller, a method comprising the steps of loading a flash memory upgrade program containing a new flash memory image and a digital signature into a portion of the system memory; configuring the memory controller to limit the processor to accessing only the flash memory and the portion of the system memory; verifying the flash memory update program using the digital signature; and, updating the flash memory only if the flash memory upgrade program is authentic.

Abstract: In a computer system having a processor, a system memory, a flash memory, and a memory controller, a method comprising the steps of loading a flash memory upgrade program containing a new flash memory image and a digital signature into a portion of the system memory; configuring the memory controller to limit the processor to accessing only the flash memory and the portion of the system memory; verifying the flash memory update program using the digital signature; and, updating the flash memory only if the flash memory upgrade program is authentic.

Abstract: In a computer system having a processor, a system memory, a flash memory, and a memory controller, a method comprising the steps of loading a flash memory upgrade program containing a new flash memory image and a digital signature into a portion of the system memory; configuring the memory controller to limit the processor to accessing only the flash memory and the portion of the system memory; verifying the flash memory update program using the digital signature; and, updating the flash memory only if the flash memory upgrade program is authentic.

Abstract: An image sensor array for capturing a sequence of video frames has a plurality of pixels, wherein each one of the pixels has a set of intrapixel logic including a previous register to store a pixel value of a previous frame and a current register to store a pixel value of a current frame, the current registers corresponding to the previous registers. An intrapixel subtractor coupled to the previous and current registers produces a difference between the previous and current registers for all pixels in the video frames in parallel. The differences are accumulated for each block of the image sensor array to form a total divergence for each block. The total divergences, associated motion vectors, and pixel values are used in motion estimation processing by a processor coupled to the image sensor array.

Abstract: In a computer system including a processor, a system memory, a flash memory, and a memory controller, memory address/window detector coupled to the processor, the memory controller, a first input of a OR logic gate and a first input of an AND gate. The OR logic gate has an output coupled to the memory controller and a second input for receiving a system memory access enable signal. Also included is a memory window control coupled to the system memory, the memory controller, the flash memory, the memory address/window detector, an output of a NOT logic gate and a first input of another AND logic gate. The additional AND logic gate has a second input for receiving a flash memory programming enable signal. A system memory access enable register is included and is coupled to an output of the first AND logic gate, a second input of the OR logic gate, and an input of the NOT logic gate. The memory window control is only accessible when the system memory access enable register is set to disabled.

Abstract: A memory comprising an addressing circuit is provided. The addressing circuit comprises at least one sequential shift register and at least one corresponding logic gate and at least one corresponding word flag cell coupled to each of the memory word lines. Enablement of the each memory word line depends upon the state of the word flag cell. In an alternate embodiment, a method for accessing a nonvolatile writeable memory is provided. The method comprises determining at least one non-operational memory bit cell of a nonvolatile writeable memory. At least one non-operational word line of the nonvolatile writeable memory is masked out, wherein the at least one non-operational word line contains the at least one non-operational memory bit cell. The nonvolatile writeable memory is sequentially addressed in read and write cycles, wherein the at least one non-operational word line is bypassed.

Abstract: In a computer system having a processor, a system memory, a flash memory, and a memory controller, a method comprising the steps of loading a flash memory upgrade program containing a new flash memory image and a digital signature into a portion of the system memory; configuring the memory controller to limit the processor to accessing only the flash memory and the portion of the system memory; verifying the flash memory update program using the digital signature; and, updating the flash memory only if the flash memory upgrade program is authentic.

Abstract: A VGA controller using address translation logic to drive a dual scan LCD panel is disclosed. The address translation logic converts the display data into an interleaved format in the display buffer, allowing the VGA controller to simultaneously access the display data for both LCD inputs without the need for a separate half-frame buffer memory. Elimination of this half-frame buffer memory reduces system cost with no reduction in performance of the VGA controller.

Abstract: A circuit for generating multiple clock edges from a single input clock is disclosed. This circuit has a digital clock input which causes a capacitor to charge and discharge with constant current sources, providing a linear voltage ramp. This linear voltage ramp is monitored by several comparators, each of which have a different reference voltage level, the outputs of which provide the multiple clock edges needed. In this manner, several outputs are generated, each of which has the same fundamental frequency as the input clock signal, but with varying duty cycles and delays from the clock edges of the input clock. In this manner, several clock edges are available for use in synchronous digital systems such as state machines that require precise timing relationships between inputs and clock signals.

Abstract: A computer display system and method is disclosed which allows a display controller in the display system to use a block of system memory rather than a dedicated frame buffer for display modes that do not require the bandwidth or the memory size of a dedicated frame buffer. The display system of the present invention includes an optional dedicated frame buffer to allow the display controller to support display modes that require the performance of the dedicated frame buffer, while retaining the capability to use system memory as a frame buffer for display modes that would only partially use the dedicated frame buffer.

Abstract: An improved VGA Controller with Arbitration Logic and method therefor is provided to enhance system performance by efficiently using the minimum amount of bus bandwidth required. This Controller includes a bus to the Frame Buffer that either the system CPU or the Display Controller may access and control. The Display Controller includes a Display FIFO which stores display data from the Frame Buffer for the Display Controller to use. This Display FIFO coupled with the Arbitration Logic makes it possible for the Display Controller to continue to output display data even when the system CPU is accessing the display data in the Frame Buffer. The Arbitration Logic attempts to keep the Display FIFO as full as possible such that a bus request by the system CPU can be immediately granted when received.

Abstract: A device and method for converting 18-bit RGB data to 5-bit gray scale data is disclosed. This device and method comprises a barrel shifter, an adder, a palette storage register, and control logic. The red data is loaded first into the barrel shifter, and is shifted, added and stored in the palette storage register. The green data is then loaded into the barrel shifter and is shifted and added to the value stored in the palette storage register. The blue data is then loaded into the barrel shifter and is shifted and added to the value stored in the palette storage register, thereby completing the conversion. The five most significant bits of the six-bit palette storage register are output as gray scale data. The shifting and adding of these six-bit integers allow a binary approximation of the appropriate coefficients for each block of color data.

Abstract: A dual edge-triggered digital storage element is disclosed. This storage element operates much like a standard digital latch, with the exception that the data input is clocked to the output on both the rising and the falling edge of the clock input. This allows the frequency of the clock signal to be reduced by half, reducing system complexity and reducing power consumption.

Abstract: A circuit allows for improved flexibility in the timing of device output, for example, from a state machine. Output for the device is placed in a first register. The output is forwarded from the first register to a second register. The first register and the second register are clocked on different edges of a clock signal. A selector selects contents of the first register or contents of the second register as the device output for an external device. The selector may be controlled by the contents of one or more flip-flops. When the device is a state machine, the output of each flip-flop may also be used as feedback to the state machine.