Patents by Inventor Phillip E. Thompson
Phillip E. Thompson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090020748Abstract: Some disclosed interband tunneling diodes comprise a plurality of substantially coherently strained layers including layers selected from a group consisting of silicon, germanium, and alloys of silicon and germanium, wherein at least one of said substantially coherently strained layers is tensile strained. Some disclosed resonant interband tunneling diodes comprise a plurality of substantially coherently strained layers including layers selected from a group consisting of silicon, germanium, and alloys of silicon and germanium, wherein at least one of said substantially coherently strained layers defines a barrier to non-resonant tunnel current. Some disclosed interband tunneling diodes comprise a plurality of substantially coherently strained layers, wherein at least one of said substantially coherently strained layers is tensile strained.Type: ApplicationFiled: July 17, 2008Publication date: January 22, 2009Applicant: THE OHIO STATE UNIVERSITY RESEARCH FOUNDATIONInventors: Niu JIN, Paul R. Berger, Phillip E. Thompson
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Patent number: 7361943Abstract: A Si-based diode (10, 10?, 100) is formed by epitaxially depositing a Si-based diode structure on a silicon substrate. The Si-based diode structure includes a Si-based pn junction (16, 16?, 18, 18?, 30, 32, 160, 161) having a backward diode current-voltage characteristic in which the forward tunneling current is substantially smaller than the backward tunneling current at comparable voltage levels. In some embodiments, the Si-based pn junction includes at least one non-silicon or silicon alloy layer such as at least one SiGe layer (16, 16?, 160, 161). In some embodiments, at least one delta doping (30, 32) is disposed on the silicon substrate in or near the pn junction, that together with the Si-based pn junction define an electrical junction having the backward diode current-voltage characteristic. A large area detector array may include a plurality of such Si-based diodes (10, 10?, 100).Type: GrantFiled: April 19, 2006Date of Patent: April 22, 2008Assignees: The Ohio State University, The United States of America, as represented by the Secretary of the NavyInventors: Paul R. Berger, Niu Jin, Phillip E. Thompson, Sung-Yong Chung
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Patent number: 7303969Abstract: Interband tunnel diodes which are compatible with Si-based processes such as, but not limited to, CMOS and SiGe HBT fabrication. Interband tunnel diodes are disclosed (i) with spacer layers surrounding a tunnel barrier; (ii) with a quantum well adjacent to, but not necessarily in contact with, one of the injectors, and (iii) with a first quantum well adjacent to, but not necessarily in contact with, the bottom injector and a second quantum well adjacent to, but not necessarily in contact with, the top injector. Process parameters include temperature process for growth, deposition or conversion of the tunnel diode and subsequent thermal cycling which to improve device benchmarks such as peak current density and the peak-to-valley current ratio.Type: GrantFiled: August 21, 2001Date of Patent: December 4, 2007Assignee: The Ohio State UniversityInventors: Paul R. Berger, Phillip E. Thompson, Roger Lake, Karl Hobart, Sean L. Rommel
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Patent number: 7297990Abstract: A silicon-based interband tunneling diode (10, 110) includes a degenerate p-type doping (22, 130) of acceptors, a degenerate n-type doping (32, 118) of donors disposed on a first side of the degenerate p-type doping (22, 130), and a barrier silicon-germanium layer (20, 136) disposed on a second side of the degenerate p-type doping (22, 130) opposite the first side. The barrier silicon-germanium layer (20, 136) suppresses diffusion of acceptors away from a p/n junction defined by the degenerate p-type and n-type dopings (22, 32, 118, 130).Type: GrantFiled: July 30, 2004Date of Patent: November 20, 2007Assignee: The Ohio State UniversityInventors: Paul R. Berger, Phillip E. Thompson, Niu Jin
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Patent number: 6803598Abstract: Interband tunnel diodes which are compatible with Si-based processes such as, but not limited to, CMOS and SiGe HBT fabrication. Interband tunnel diodes are disclosed (i) with spacer layers surrounding a tunnel barrier; (ii) with a quantum well adjacent to, but not necessarily in contact with, one of the injectors, and (iii) with a first quantum well adjacent to, but not necessarily in contact with, the bottom injector and a second quantum well adjacent to, but not necessarily in contact with, the top injector. Process parameters include temperature process for growth, deposition or conversion of the tunnel diode and subsequent thermal cycling which to improve device benchmarks such as peak current density and the peak-to-valley current ratio.Type: GrantFiled: May 5, 2000Date of Patent: October 12, 2004Assignee: University of DelawareInventors: Paul R. Berger, Phillip E. Thompson, Roger Lake, Karl Hobart, Sean L. Rommel
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Publication number: 20030049894Abstract: Interband tunnel diodes which are compatible with Si-based processes such as, but not limited to, CMOS and SiGe HBT fabrication. Interband tunnel diodes are disclosed (i) with spacer layers surrounding a tunnel barrier; (ii) with a quantum well adjacent to, but not necessarily in contact with, one of the injectors, and (iii) with a first quantum well adjacent to, but not necessarily in contact with, the bottom injector and a second quantum well adjacent to, but not necessarily in contact with, the top injector. Process parameters include temperature process for growth, deposition or conversion of the tunnel diode and subsequent thermal cycling which to improve device benchmarks such as peak current density and the peak-to-valley current ratio.Type: ApplicationFiled: August 21, 2001Publication date: March 13, 2003Applicant: University of DelawareInventors: Paul R. Berger, Phillip E. Thompson, Roger Lake, Karl Hobart, Sean L. Rommel
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Patent number: 6201342Abstract: An electron emitting device characterized by a monocrystalline substrate, a plurality of monocrystalline nanomesas or pillars disposed on the substrate in a spaced relationship and extending generally normally therefrom, monocrystalline self-assembled tips disposed on top of the nanomesas, and essentially atomically sharp apexes on the tips for field emitting electrons. A method for making the emitters is characterized by forming a gate electrode and gate electrode apertures before forming the tips on the nanomesas.Type: GrantFiled: June 30, 1997Date of Patent: March 13, 2001Assignee: The United States of America as represented by the Secretary of the NavyInventors: Karl D. Hobart, Francis J. Kub, Henry F. Gray, Mark E. Twigg, Phillip E. Thompson, Jonathan Shaw
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Patent number: 6113451Abstract: An electron emitting device characterized by a monocrystalline substrate, a plurality of monocrystalline nanomesas or pillars disposed on the subste in a spaced relationship and extending generally normally therefrom, monocrystalline self-assembled tips disposed on top of the nanomesas, and essentially atomically sharp apexes on the tips for field emitting electrons. A method for making the emitters is characterized by forming a gate electrode and gate electrode apertures before forming the tips on the nanomesas.Type: GrantFiled: December 22, 1999Date of Patent: September 5, 2000Assignee: The United State of America as represented by the Secretary of the NavyInventors: Karl D. Hobart, Francis J. Kub, Henry F. Gray, Mark E. Twigg, Phillip E. Thompson, Jonathan Shaw
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Patent number: 5103280Abstract: A photoconductive semiconductor device having a source, a drain, and a photosensitive channel therebetween. The channel has a surface layer that is highly doped with respect to the remainder of the channel, compensating at least in part for the channel's surface depletion layer. In this manner, the photosensitivity of the device is increased without disproportionately increasing wasted dark current. In a preferred embodiment, the additional doping of the channel's surface layer is done by ion implantation, and the device is a monolith formed of gallium arsenide.Type: GrantFiled: June 29, 1988Date of Patent: April 7, 1992Assignee: The United States of America as represented by the Secretary of the NavyInventors: Phillip E. Thompson, Nicolas A. Papanicolaou, J. Bradley Boos
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Patent number: 4673446Abstract: An InP wafer, comprising a S.I. InP substrate, a n-type InP active layer disposed on the substrate and oxygen implanted isolation regions disposed in the active layer.Type: GrantFiled: December 12, 1985Date of Patent: June 16, 1987Assignee: The United States of America as represented by the Secretary of the NavyInventors: Phillip E. Thompson, Harry B. Dietrich