Abstract: A high performance computer graphics image computation system architecture is disclosed. The system architecture includes a computational processor ring which includes a plurality of closely coupled computational subsystems. The computational subsystems operate asynchronously and each is interconnected with two adjacent computational subsystems. The architecture of the processor ring allows rapid communication between the computational subsystems while avoiding a deadlock condition. The system architecture also includes a video processor ring wherein a plurality of video processors are synchronously linked together. A plurality of local communication paths couple the computational subsystems to the video processors. The video processor ring is able to move massive amounts of data, in the form of digital video signals, from various points within the system.

Abstract: An electronic data processing pipeline system and method for processing encoded control points representing graphical illustrations. The pipeline comprises a number of separate micro-programmed circuit cards, each of which are programmed to perform a specific processing operation.A command is first sent to a matrix maker card defining a geometrical transformation to be performed on the graphical illustration. The matrix maker card, together with a matrix multiplier card, then calculates a transformation matrix representing the desired transformation.Electronic representations of control data points are then transmitted to the pipeline for processing. These control points are 3D points comprising both the vertices which terminate linear edges of the illustration and the control points corresponding to curved edges of the illustration. Each of the points is encoded to indicate whether it represents a vertex or a control point for a curved edge.