Patents by Inventor Phillip Paul Normand

Phillip Paul Normand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Programmable delay method for hierarchical signal balancing
    Patent number: 7073145
    Abstract: A method for signal balancing across multiple random logic macros. The method inserts a programmable delay element into the design before the last buffer level on all signal paths. The random logic macro is then fully designed including cell placement and wiring. With programmable delay buffers in place, the random logic macros may be used within multiple designs, each having varying signal latency requirements.
    Type: Grant
    Filed: January 7, 2003
    Date of Patent: July 4, 2006
    Assignee: International Business Machines Corporation
    Inventors: Thomas W. Fry, Daniel R. Menard, Phillip Paul Normand
  • Signal balancing between voltage domains
    Patent number: 6986116
    Abstract: A method for balancing signals across an IC design having multiple voltage domains. The method uses a voltage tress to balance the signals at the top level above the voltage domains. Then using worst case and best case signal latencies determines the average latency in each voltage domain. Then balancing signals at the other levels of the design by incrementing the latencies in each domain until a target level based on the slowest average latency is reached.
    Type: Grant
    Filed: January 7, 2003
    Date of Patent: January 10, 2006
    Assignee: International Business Machines Corporation
    Inventors: Thomas Walker Fry, Daniel Richard Menard, Phillip Paul Normand
  • SIGNAL BALANCING BETWEEN VOLTAGE DOMAINS
    Publication number: 20040133865
    Abstract: A method for balancing signals across an IC design having multiple voltage domains. The method uses a voltage tress to balance the signals at the top level above the voltage domains. Then using worst case and best case signal latencies determines the average latency in each voltage domain. Then balancing signals at the other levels of the design by incrementing the latencies in each domain until a target level based on the slowest average latency is reached.
    Type: Application
    Filed: January 7, 2003
    Publication date: July 8, 2004
    Applicant: International Business Machines Corporation
    Inventors: Thomas Walker Fry, Daniel Richard Menard, Phillip Paul Normand
  • PROGRAMMABLE DELAY METHOD FOR HIERARCHICAL SIGNAL BALANCING
    Publication number: 20040133864
    Abstract: A method for signal balancing across multiple random logic macros. The method inserts a programmable delay element into the design before the last buffer level on all signal paths. The random logic macro is then fully designed including cell placement and wiring. With programmable delay buffers in place, the random logic macros may be used within multiple designs, each having varying signal latency requirements.
    Type: Application
    Filed: January 7, 2003
    Publication date: July 8, 2004
    Applicant: International Business Machines Corporation
    Inventors: Thomas Walker Fry, Daniel Richard Menard, Phillip Paul Normand