Abstract: A method of preparing a computer processor die includes determining a warpage shape of the computer processor die at a testing temperature. The method also includes selectively contouring a thickness of the computer processor die at a contouring temperature by physically removing material from a surface of the computer processor die such that the surface will be substantially flat at the testing temperature.

Abstract: A method of preparing a computer processor die includes determining a warpage shape of the computer processor die at a testing temperature. The method also includes selectively contouring a thickness of the computer processor die at a contouring temperature by physically removing material from a surface of the computer processor die such that the surface will be substantially flat at the testing temperature.

Abstract: Embodiments are directed to a computer implemented method and system for the testing, characterization and diagnostics of integrated circuits. A system might include a device under test, such as an integrated circuit, that includes an adaptive microcontroller. The method includes loading a testing program for execution by the adaptive microcontroller, causing the microcontroller to execute the testing program. Once results from the testing program are received, the testing program can be adaptively modified based on the results. The modified testing program can be run again. The testing program can modify parameters of the integrated circuit that are not externally accessible. Other embodiments are also disclosed.

Abstract: Techniques relate to an interactive logic diagnostic process. A diagnostic iteration loop is performed. When a critical failure does not have the diagnostic resolution that meets a predefined diagnostic resolution, potential faults related to the critical failure are isolated. When the critical failure has a diagnostic resolution that meets the predefined diagnostic resolution, the diagnostic iteration loop ends. Path focused fault test patterns are applied to the device under test in order to generate updated results of the path focused fault test patterns, such that the diagnostic resolution has been increased because a number of the potential faults related to the critical failure has decreased, and/or a size of a physical area of the potential faults related to the critical failure has decreased. The diagnostic iteration loop is returned to.

Abstract: Techniques relate to dynamic complex fault model generation for diagnostics simulation and pattern generation. Inline fabrication parametric data is received, and the inline fabrication parametric data is a collection of physical measurements made on a device under test during a manufacturing fabrication of the device under test. A fault model of defects is generated according to the inline fabrication parametric data, where the fault model is based on a physical design of the device under test combined with the inline fabrication parametric data for the device under test. Test patterns are generated based on the fault model and the inline fabrication parametric data, such that the test patterns are configured to test the device under test in order to obtain results that are based on the inline fabrication parametric data. A simulation is run of the device under test using the results and the inline fabrication parametric data.

Abstract: Techniques relate to an interactive logic diagnostic process. A diagnostic iteration loop is performed. When a critical failure does not have the diagnostic resolution that meets a predefined diagnostic resolution, potential faults related to the critical failure are isolated. When the critical failure has a diagnostic resolution that meets the predefined diagnostic resolution, the diagnostic iteration loop ends. Path focused fault test patterns are applied to the device under test in order to generate updated results of the path focused fault test patterns, such that the diagnostic resolution has been increased because a number of the potential faults related to the critical failure has decreased, and/or a size of a physical area of the potential faults related to the critical failure has decreased. The diagnostic iteration loop is returned to.

Abstract: Techniques relate to an interactive logic diagnostic process. A diagnostic iteration loop is performed. When a critical failure does not have the diagnostic resolution that meets a predefined diagnostic resolution, potential faults related to the critical failure are isolated. When the critical failure has a diagnostic resolution that meets the predefined diagnostic resolution, the diagnostic iteration loop ends. Path focused fault test patterns are applied to the device under test in order to generate updated results of the path focused fault test patterns, such that the diagnostic resolution has been increased because a number of the potential faults related to the critical failure has decreased, and/or a size of a physical area of the potential faults related to the critical failure has decreased. The diagnostic iteration loop is returned to.

Abstract: Techniques relate to dynamic complex fault model generation for diagnostics simulation and pattern generation. Inline fabrication parametric data is received, and the inline fabrication parametric data is a collection of physical measurements made on a device under test during a manufacturing fabrication of the device under test. A fault model of defects is generated according to the inline fabrication parametric data, where the fault model is based on a physical design of the device under test combined with the inline fabrication parametric data for the device under test. Test patterns are generated based on the fault model and the inline fabrication parametric data, such that the test patterns are configured to test the device under test in order to obtain results that are based on the inline fabrication parametric data. A simulation is run of the device under test using the results and the inline fabrication parametric data.

Abstract: Techniques relate to dynamic complex fault model generation for diagnostics simulation and pattern generation. Inline fabrication parametric data is received, and the inline fabrication parametric data is a collection of physical measurements made on a device under test during a manufacturing fabrication of the device under test. A fault model of defects is generated according to the inline fabrication parametric data, where the fault model is based on a physical design of the device under test combined with the inline fabrication parametric data for the device under test. Test patterns are generated based on the fault model and the inline fabrication parametric data, such that the test patterns are configured to test the device under test in order to obtain results that are based on the inline fabrication parametric data. A simulation is run of the device under test using the results and the inline fabrication parametric data.

Abstract: Embodiments are directed to a computer implemented method and system for the testing, characterization and diagnostics of integrated circuits. A system might include a device under test, such as an integrated circuit, that includes an adaptive microcontroller. The method includes loading a testing program for execution by the adaptive microcontroller, causing the microcontroller to execute the testing program. Once results from the testing program are received, the testing program can be adaptively modified based on the results. The modified testing program can be run again. The testing program can modify parameters of the integrated circuit that are not externally accessible. Other embodiments are also disclosed.

Abstract: Techniques relate to an interactive logic diagnostic process. A diagnostic iteration loop is performed. When a critical failure does not have the diagnostic resolution that meets a predefined diagnostic resolution, potential faults related to the critical failure are isolated. When the critical failure has a diagnostic resolution that meets the predefined diagnostic resolution, the diagnostic iteration loop ends. Path focused fault test patterns are applied to the device under test in order to generate updated results of the path focused fault test patterns, such that the diagnostic resolution has been increased because a number of the potential faults related to the critical failure has decreased, and/or a size of a physical area of the potential faults related to the critical failure has decreased. The diagnostic iteration loop is returned to.

Abstract: Techniques relate to dynamic complex fault model generation for diagnostics simulation and pattern generation. Inline fabrication parametric data is received, and the inline fabrication parametric data is a collection of physical measurements made on a device under test during a manufacturing fabrication of the device under test. A fault model of defects is generated according to the inline fabrication parametric data, where the fault model is based on a physical design of the device under test combined with the inline fabrication parametric data for the device under test. Test patterns are generated based on the fault model and the inline fabrication parametric data, such that the test patterns are configured to test the device under test in order to obtain results that are based on the inline fabrication parametric data. A simulation is run of the device under test using the results and the inline fabrication parametric data.

Abstract: Techniques relate to dynamic complex fault model generation for diagnostics simulation and pattern generation. Inline fabrication parametric data is received, and the inline fabrication parametric data is a collection of physical measurements made on a device under test during a manufacturing fabrication of the device under test. A fault model of defects is generated according to the inline fabrication parametric data, where the fault model is based on a physical design of the device under test combined with the inline fabrication parametric data for the device under test. Test patterns are generated based on the fault model and the inline fabrication parametric data, such that the test patterns are configured to test the device under test in order to obtain results that are based on the inline fabrication parametric data. A simulation is run of the device under test using the results and the inline fabrication parametric data.

Abstract: A method, apparatus and computer program product are provided for implementing diagnostics of transitional scan chain defects using structural Logic Built In Self Test (LBIST) test patterns. A LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a passing operating region and scan data is unloaded. The LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a failing operating region for the device under test and scan data is unloaded. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system.

Abstract: A method, apparatus and computer program product are provided for implementing isolation of VLSI AC scan chain defects using structural Array Built In Self Test (ABIST) test patterns. An ABIST test pattern is applied to the device under test and multiple ABIST array algorithms are applied in a passing operating region and each scan chain is unloaded. The ABIST test pattern is applied to the device under test and multiple ABIST array algorithms are applied in a failing operating region for the device under test. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system.

Abstract: A method for performing a logical built-in self-test of an integrated circuit is disclosed. The method includes performing a flush and scan test to determine whether the scan chains function correctly. If one of the scan chains does not function correctly, the logical built-in self-test is terminated. If each of the scan chains functions correctly, a structural test of the design-for-test logic supporting LBIST is performed to determine whether the LBIST design-for-test logic functions correctly. If the LBIST design-for-test logic does not function correctly, the logical built-in self-test is terminated. If the LBIST design-for-test logic functions correctly, a level sensitive scan design test of the functional combinational logic is performed using the logic supporting LBIST design-for-test to determine if the integrated circuit functions correctly.

Abstract: A method for implementing at speed bit fail mapping of an embedded memory system having ABIST (Array Built In Self Testing), comprises using a high speed multiplied clock which is a multiple of an external clock of an external tester to sequence ABIST bit fail testing of the embedded memory system. Collect store fail data during ABIST testing of the embedded memory system. Perform a predetermined number of ABIST runs before issuing a bypass order substituting the external clock for the high speed multiplied clock. Use the external clock of the tester to read bit fail data out to the external tester.

Abstract: A method, system and computer program product for testing the Design-For-Testability/Design-For-Diagnostics (DFT/DFD) and supporting BIST functions of a custom microcode array. Upon completion of the LSSD Flush and Scan tests, the ABIST program is applied to target the logic associated direct current (DC) and alternating current (AC) faults of ABIST array Design-For-Testability/Design-For-Diagnostics DFT/DFD functions that support the microcode array. A LSSD test of the DFT functional combinational logic is performed by applying generated LSSD deterministic test patterns targeting the ABIST design-for-test faults to determine if the DFT supporting the microcode array is functioning correctly. Additional tests may be terminated upon resulting failure of the applied ABIST DFT circuitry surrounding the arrays.

Abstract: A structural design-for-test for diagnosing broken scan chain defects of long non-scannable register chains (GPTR) The GPTR and the system for testing and diagnosing the broken LSSD scan-only chains rapidly localize defects to the failing Shift Register Latch (SRL) pair. The GPTR modifies the latches used in the GPTR scan chain to standard LSSD L1/L2 master-slave SRL type latch pairs; connects all the system ports of the L1 latches to the Shift Register Input (SRI) and clocked by the system C1-clk while the L1 scan port is clocked by the A-clk and L2 scan port is clocked only by the B-clk. The L1 latches are connected to at least one multiplexer having a first output connected to an input of each odd SRL, and a second output connected to an input port of each even SRL.

Abstract: This invention involves the use of the JTAG functional test patterns and exercisors to solve the problem of diagnosing broken scan chains in either a serial or a lateral broadside insertion manner across all latch system ports and to analyze the response data efficiently for the purpose of readily identifying switching and non-switching latches with the next to last non-switching latch being the point of the break within a defective scan chain(s). This comprehensive latch perturbation, in conjunction with iterative diagnostic algorithms is used to identify and to pinpoint the defective location in such a broken scan chain(s). This JTAG Functional test function and the JTAG test patterns ultimately derived therefrom, can take on different forms and origins, some external to a product and some internal to a product.