Abstract: A transceiver 400 is provided in an ultrawide bandwidth device, which includes an antenna 110, a transmitter circuit 145, and a receiver circuit 165. A transmitter amplifier 440 is provided between the antenna 110 and the transmitter circuit 145, and is configured to have an operational transmitter output impedance when the transceiver 400 is in a transmit mode and an isolation transmitter output impedance when the transceiver 400 is in a receive mode. A receiver amplifier 460 is provided between the antenna 110 and the receiver circuit 165, and is configured to have an operational receiver input impedance when the transceiver 400 is in a receive mode and an isolation receiver input impedance when the transceiver 400 is in a transmit mode. The isolation transmitter output impedance is greater than the operational receiver input impedance, and the isolation receiver input impedance is greater than the operational transmitter output impedance.

Abstract: An ultra wideband direct sequence code division multiple access (UWB DS-CDMA) (101) transmitter is provided. It includes a first multiplier (125) receiving two input signals, where the input signals are selected from a multi-level code signal (117), a transmit data signal (123), and a radio frequency (RF) center frequency signal (121), and responsive to the two input signals, generating a combined signal (127). Further included is a network (119) receiving a code-clock signal (113) aligned with the multi-level signal (117), multiplying the frequency of the code-clock signal (113) by a factor, and responsive thereto, producing the RF center frequency signal (121). Also provided is a second multiplier (129) receiving the combined signal (127) and the other of the input signals (117, 123, 121), and responsive thereto, generating an output signal (131).

Abstract: A method is provided for generating a multiple band ultrawide bandwidth signal. In this method, an ultrawide bandwidth devices provides a first reference signal having a first reference frequency, and a second reference signal having a second reference frequency that is different from the first reference frequency. The device generates a first ultrawide bandwidth signal based on the first reference signal, and a second ultrawide bandwidth signal based on the second reference signal, creating two separate frequency bands. These two signals can be generated form the same base clock signal, allowing for significantly simpler implementation and modification.

Abstract: A circuit for adjusting a magnitude of a transmit signal includes a transmitter (105), providing a transmit signal (107). It also includes a transmitter amplifier (109), receiving the transmit signal (107) and a power control adjustment signal (121), and responsive thereto, providing an amplified transmit signal (111). The circuit also includes a detector (123), for detecting an amplitude of the amplified transmit signal (111). Also included is an error component (137) for determining the difference between the amplitude and a reference level (129). Further provided is a digital signal generator (155), receiving the difference (145), and responsive thereto, generating (157) a reference signal (125) and the power control adjustment signal (117, 121), where the reference level (129) is responsive to the reference signal (125).

Abstract: A method (700, 1100) and apparatus (300) are provided in a receiver for applying a variable gain to a received signal including a transmitted codeword in accordance with an Ultra Wideband (UWB) protocol. A first signal is generated and input to a selectable gain stage including a series of selectable 0 dB and 9 dB gain elements (302-305). The first signal includes the received signal mixed with a local oscillator signal modified according to a reference codeword. A gain value is selected from the selectable gain stage to amplify the first signal and form a second signal. An output signal is generated by combining the second signal and the modified local oscillator signal.

Abstract: A bandpass-sampling analog-to-digital demodulator (BS-ADD) is provided. A radio frequency (RF) signal is received by a junction summer, which subtracts a feedback signal from the RF signal to produce an error signal. The error signal is then bandpassed and amplified by the RF bandpass filter/amplifier. The amplified signal is bandpass-sampled by a low-resolution analog-to-digital converter, and is demodulated and converted into a high-resolution digital signal. The down converted signal is multiplied with a clock to be up-converted back to the radio frequency. The resulting multiplied signal is converted to an analog signal and fed back to the junction summer.

Abstract: A method and an apparatus are provided for mitigating spectral lines in a wireless signal. First a code word is generated that is made up of a plurality of binary or ternary encoded pulses. Then a plurality of code-word-modulated wavelets are generated in response to the code word. These wavelets can be Gaussian monopulses, repeated cycles of a sine wave, or other shaped impulse signals. The plurality of code-word-modulated wavelets are then modulated with a bit of transmit data to form a plurality of data-modulated wavelets. This modulation serves to whiten the signals since the transmit data is effectively random. Finally, the plurality of data-modulated wavelets are transmitted to a remote device.

Abstract: A mono-cycle generating circuit includes a multiplexer, a pulse generating circuit, and a buffer circuit. The multiplexer receives data of a logical 1 or a logical 0, determines whether to generate a positive mono-cycle or a negative mono-cycle, based upon the data, and outputs clock signals varying in time based upon the data. The pulse generating circuit is coupled to the multiplexer, receives the clock signals and generates a first series of pulses including an up-pulse preceding a down-pulse, or a second series of pulses including a down-pulse preceding an up-pulse, in response to the clock signals received by the multiplexer. The buffer circuit is coupled to the pulse generating circuit and includes a switch circuit and a common mode buffer. The switch circuit generates the positive mono-cycle or the negative mono-cycle, based upon whether the first series of pulses is received from the pulse generating circuit or the second series of pulses is received from the pulse generating circuit.

Abstract: A monocycle forming network may include a monocycle generator, up and down pulse generators, data modulators and clock generation circuits. The network may generate monocycle pulses having very narrow pulse widths, approximately 80 picoseconds peak to peak. The monocycles may be modulated to carry data in ultra-wideband communication systems.

Abstract: A mono-cycle generating circuit includes a multiplexer, a pulse generating circuit, and a buffer circuit. The multiplexer receives data of a logical 1 or a logical 0, determines whether to generate a positive mono-cycle or a negative mono-cycle, based upon the data, and outputs clock signals varying in time based upon the data. The pulse generating circuit is coupled to the multiplexer, receives the clock signals and generates a first series of pulses including an up-pulse preceding a down-pulse, or a second series of pulses including a down-pulse preceding an up-pulse, in response to the clock signals received by the multiplexer. The buffer circuit is coupled to the pulse generating circuit and includes a switch circuit and a common mode buffer. The switch circuit generates the positive mono-cycle or the negative mono-cycle, based upon whether the first series of pulses is received from the pulse generating circuit or the second series of pulses is received from the pulse generating circuit.

Abstract: A switched capacitor amplifier includes a pair of output capacitors, providing high throughput suitable for pipestaged circuit applications. During operation, the amplifiers may generate an evaluation output once per clock cycle. During a first clock cycle, one of the two output capacitors holds an evaluation potential to be output from the amplifier and the second output capacitor both precharges and evaluates. During a second clock cycle, the roles of the output capacitors reverse and the second output capacitor holds the evaluation potential and the first output capacitor precharges and evaluates. The invention is suitable for use with a variety of amplifier topologies.

Abstract: A mono-cycle generating circuit comprises a control circuit, a multiplexer, and a driver switch circuit. The control circuit generates sets of timing pulses. The multiplexer selects one of the sets of timing pulses. The driver switch circuit outputs a mono-cycle based upon the selected set of timing pulses. The driver switch circuit comprises complementary sets of switches, each complementary set of switches including complementary amplitude pull-up/pull-down functions such that the output mono-cycle is a full rail swing mono-cycle.

Abstract: A switched capacitor amplifier includes a pair of output capacitors, providing high throughput suitable for pipestaged circuit applications. During operation, the amplifiers may generate an evaluation output once per clock cycle. During a first clock cycle, one of the two output capacitors holds an evaluation potential to be output from the amplifier and the second output capacitor both precharges and evaluates. During a second clock cycle, the roles of the output capacitors reverse and the second output capacitor holds the evaluation potential and the first output capacitor precharges and evaluates. The invention is suitable for use with a variety of amplifier topologies.

Abstract: A mono-cycle generating circuit includes a multiplexer, a pulse generating circuit, and a buffer circuit. The multiplexer receives data of a logical 1 or a logical 0, determines whether to generate a positive mono-cycle or a negative mono-cycle, based upon the data, and outputs clock signals varying in time based upon the data. The pulse generating circuit is coupled to the multiplexer, receives the clock signals and generates a first series of pulses including an up-pulse preceding a down-pulse, or a second series of pulses including a down-pulse preceding an up-pulse, in response to the clock signals received by the multiplexer. The buffer circuit is coupled to the pulse generating circuit and includes a switch circuit and a common mode buffer. The switch circuit generates the positive mono-cycle or the negative mono-cycle, based upon whether the first series of pulses is received from the pulse generating circuit or the second series of pulses is received from the pulse generating circuit.

Abstract: A mono-cycle generating circuit comprises a control circuit, a multiplexer, and a driver switch circuit. The control circuit generates sets of timing pulses. The multiplexer selects one of the sets of timing pulses. The driver switch circuit outputs a mono-cycle based upon the selected set of timing pulses. The driver switch circuit comprises complementary sets of switches, each complementary set of switches including complementary amplitude pull-up/pull-down functions such that the output mono-cycle is a full rail swing mono-cycle.

Abstract: A monocycle forming network may include a monocycle generator, up and down pulse generators, data modulators and clock generation circuits. The network may generate monocycle pulses having very narrow pulse widths, approximately 80 picoseconds peak to peak. The monocycles may be modulated to carry data in ultra-wideband communication systems.

Abstract: A method and circuit for detecting arc instabilities in a high pressure gas discharge lamp. The method and circuit rectify and low pass filter the lamp voltage to obtain a quasi-rms voltage having recurrent periods with first zones containing spurious noise from switching of inverter switches and broad second zones, between the first zones, which are substantially free of spurious noise. The quasi-rms voltage is sampled only during the second zones, so that the samples have a high information-to-noise ratio. The sample signal may be used in a variety of methods to detect and control arc instabilities in gas discharge lamps.

Abstract: A ballast for a high intensity discharge lamp which detects the onset of acoustic resonance instability by detecting an asymmetry in a signal which is otherwise symmetric in the absence of such instability. The AC supply ripple voltage, which is normally present in the lamp current, exhibits symmetry in the absence of acoustic resonance, and becomes substantially asymmetric at the onset of acoustic resonance. By measuring the duration of each half cycle in the ripple voltage, an asymmetry in the ripple voltage can be easily and rapidly detected, and the operating frequency of the lamp current is changed before the resonance produces visually apparent flicker.

Abstract: A variable duration method for controlling a high pressure gas discharge lamp to avoid arc instabilities caused, for example, by acoustic resonance. The method controls the lamp at different operating frequencies so that it stays longer at frequencies which are stable while only staying for very short times at frequencies where the arc is unstable. The method and apparatus operate the lamp at a plurality of operating frequencies and determine a stability factor for each frequency by recurrently sampling an electrical lamp parameter during operation at each frequency. The stability factor corresponds inversely to a deviation in the sensed electrical parameter, so that frequencies with little arc instability have a high stability factor and are selected more frequently for operating the lamp than are frequencies having arc instabilities, which will have low stability factors.