Patents by Inventor Pi-Chen Shieh

Pi-Chen Shieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5923088
    Abstract: A bond pad structure and method of forming the bond pad structure which provides for reliable interconnections between the bond pad structure and the next level of circuit integration. The bond pad structure uses three metal pads separated by layers of dielectric. Via plugs are formed between the first and second metal pads and between the second and third metal pads. The via plugs are formed in a diamond shape with respect to the metal pads. The metal pads are squares with the same orientation. The periphery of the via plugs forms a square rotated 45.degree. with respect to the square metal pads.
    Type: Grant
    Filed: September 15, 1997
    Date of Patent: July 13, 1999
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ruey-Yun Shiue, Wen-Teng Wu, Pi-Chen Shieh, Chin-Kai Liu
  • Patent number: 5712207
    Abstract: A process for forming aluminum interconnect structures has been developed, that concentrates on alleviating the effects of the poor step coverage of the interconnect metallization, that develops in areas where aluminum overlies tungsten filled contact holes. A high pressure treatment of the aluminum based metallization layer is performed at pressures in the range of 50 to 120 Mega-pascal, to improve the coverage of the aluminum based layer, specifically in seams or voids in the underlying tungsten plugs.
    Type: Grant
    Filed: May 19, 1997
    Date of Patent: January 27, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Kuang Lee, Pi-Chen Shieh, Pin-Nan Tseng
  • Patent number: 5700735
    Abstract: A bond pad structure and method of forming the bond pad structure which provides for reliable interconnections between the bond pad structure and the next level of circuit integration. The bond pad structure uses three metal pads separated by layers of dielectric. Via plugs are formed between the first and second metal pads and between the second and third metal pads. The via plugs are formed in a diamond shape with respect to the metal pads. The metal pads are squares with the same orientation. The periphery of the via plugs forms a square rotated 45.degree. with respect to the square metal pads.
    Type: Grant
    Filed: August 22, 1996
    Date of Patent: December 23, 1997
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ruey-Yun Shiue, Wen-Teng Wu, Pi-Chen Shieh, Chin-Kai Liu
  • Patent number: 5547881
    Abstract: A method is described for forming a high contact resistance region within the drain region or source region of an insulated gate field effect transistor as part of a high resistance resistor for electrostatic discharge protection of the field effect transistor. The high resistance contact region is formed as part of a self aligned silicide, or salicide, contact process. Nitrogen ion implantation at the high resistance contact region into the metal which will be used to form the metal silicide low resistance contacts converts the metal at the high resistance contact region to metal nitride. Since all the metal at the high resistance contact region is converted to metal nitride there is no free metal to form metal silicide at the high resistance contact region when the low resistance metal silicide contacts are formed. Low resistance contacts to the gate electrode, source, and drain are formed using metal silicide.
    Type: Grant
    Filed: March 6, 1996
    Date of Patent: August 20, 1996
    Assignee: Taiwan Semiconductor Manufacturing Company LTD
    Inventors: Jau-Jey Wang, Pi-Chen Shieh, Pin-Nan Tseng