Patents by Inventor Pierre Caubet

Pierre Caubet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10211059
    Abstract: Local variability of the grain size of work function metal, as well as its crystal orientation, induces a variable work function and local variability of transistor threshold voltage. If the metal nitride for the work function metal of the transistor gate is deposited using a radio frequency physical vapor deposition, equiaxed grains are produced. The substantially equiaxed structure for the metal nitride work function metal layer (such as with TiN) reduces local variability in threshold voltage.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: February 19, 2019
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Pierre Caubet, Florian Domengie, Carlos Augusto Suarez Segovia, Aurelie Bajolet, Onintza Ros Bengoechea
  • Patent number: 9953837
    Abstract: A MOS transistor having a gate insulator including a dielectric of high permittivity and a conductive layer including a TiN layer, wherein the nitrogen composition in the TiN layer is sub-stoichiometric in its lower portion and progressively increases to a stoichiometric composition in its upper portion.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: April 24, 2018
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Pierre Caubet, Sylvain Baudot
  • Publication number: 20170256625
    Abstract: Local variability of the grain size of work function metal, as well as its crystal orientation, induces a variable work function and local variability of transistor threshold voltage. If the metal nitride for the work function metal of the transistor gate is deposited using a radio frequency physical vapor deposition, equiaxed grains are produced. The substantially equiaxed structure for the metal nitride work function metal layer (such as with TiN) reduces local variability in threshold voltage.
    Type: Application
    Filed: May 22, 2017
    Publication date: September 7, 2017
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Pierre Caubet, Florian Domengie, Carlos Augusto Suarez Segovia, Aurelie Bajolet, Onintza Ros Bengoechea
  • Patent number: 9691871
    Abstract: Local variability of the grain size of work function metal, as well as its crystal orientation, induces a variable work function and local variability of transistor threshold voltage. If the metal nitride for the work function metal of the transistor gate is deposited using a radio frequency physical vapor deposition, equiaxed grains are produced. The substantially equiaxed structure for the metal nitride work function metal layer (such as with TiN) reduces local variability in threshold voltage.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: June 27, 2017
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Pierre Caubet, Florian Domengie, Carlos Augusto Suarez Segovia, Aurelie Bajolet, Onintza Ros Bengoechea
  • Publication number: 20170179250
    Abstract: Local variability of the grain size of work function metal, as well as its crystal orientation, induces a variable work function and local variability of transistor threshold voltage. If the metal nitride for the work function metal of the transistor gate is deposited using a radio frequency physical vapor deposition, equiaxed grains are produced. The substantially equiaxed structure for the metal nitride work function metal layer (such as with TiN) reduces local variability in threshold voltage.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Pierre Caubet, Florian Domengie, Carlos Augusto Suarez Segovia, Aurelie Bajolet, Onintza Ros Bengoechea
  • Patent number: 9536599
    Abstract: A memory device may include an access transistor, and a memory cell configured to store an item of information. The memory cell may include first and second electrodes configured to have different optoelectronic states corresponding respectively to two values of the item of information, and to switch between the different optoelectronic states based upon a control signal external to the memory cell, the different optoelectronic states being naturally stable in an absence of the control signal. The memory cell may also include a solid electrolyte between the first and second electrodes.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: January 3, 2017
    Assignee: SMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Pierre Caubet, Mickael Gros-Jean
  • Patent number: 9530489
    Abstract: A memory device may include an access transistor, and a memory cell configured to store an item of information. The memory cell may include first and second electrodes configured to have different optoelectronic states corresponding respectively to two values of the item of information, and to switch between the different optoelectronic states based upon a control signal external to the memory cell, the different optoelectronic states being naturally stable in an absence of the control signal. The memory cell may also include a solid electrolyte between the first and second electrodes.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: December 27, 2016
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Pierre Caubet, Mickael Gros-Jean
  • Publication number: 20160372183
    Abstract: A memory device may include an access transistor, and a memory cell configured to store an item of information. The memory cell may include first and second electrodes configured to have different optoelectronic states corresponding respectively to two values of the item of information, and to switch between the different optoelectronic states based upon a control signal external to the memory cell, the different optoelectronic states being naturally stable in an absence of the control signal. The memory cell may also include a solid electrolyte between the first and second electrodes.
    Type: Application
    Filed: August 29, 2016
    Publication date: December 22, 2016
    Inventors: PIERRE CAUBET, MICKAEL GROS-JEAN
  • Patent number: 9257518
    Abstract: At least one MOS transistor is produced by forming a dielectric region above a substrate and forming a gate over the dielectric region. The gate is formed to include a metal gate region. Formation of the metal gate region includes: forming a layer of a first material configured to reduce an absolute value of a threshold voltage of the transistor, and configuring a part of the metal gate region so as also to form a diffusion barrier above the layer of the first material. Then, doped source and drain regions are formed using a dopant activation anneal.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: February 9, 2016
    Assignee: STMicrolectronics (Crolles 2) SAS
    Inventors: Sylvain Baudot, Pierre Caubet, Florian Domengie
  • Publication number: 20150200099
    Abstract: A MOS transistor having a gate insulator including a dielectric of high permittivity and a conductive layer including a TiN layer, wherein the nitrogen composition in the TiN layer is sub-stoichiometric in its lower portion and progressively increases to a stoichiometric composition in its upper portion.
    Type: Application
    Filed: March 26, 2015
    Publication date: July 16, 2015
    Inventors: PIERRE CAUBET, SYLVAIN BAUDOT
  • Patent number: 9029254
    Abstract: A method for forming an aluminum titanium nitride layer on a wafer by plasma-enhanced physical vapor deposition including a first step at a radio frequency power ranging between 100 and 500 W only, and a second step at a radio frequency power ranging between 500 and 1,000 W superimposed to a D.C. power ranging between 500 and 1,000 W. An insulated gate comprising such an aluminum titanium nitride layer.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: May 12, 2015
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Pierre Caubet, Florian Domengie, Sylvain Baudot
  • Publication number: 20150117128
    Abstract: A memory device may include an access transistor, and a memory cell configured to store an item of information. The memory cell may include first and second electrodes configured to have different optoelectronic states corresponding respectively to two values of the item of information, and to switch between the different optoelectronic states based upon a control signal external to the memory cell, the different optoelectronic states being naturally stable in an absence of the control signal. The memory cell may also include a solid electrolyte between the first and second electrodes.
    Type: Application
    Filed: October 29, 2014
    Publication date: April 30, 2015
    Inventors: Pierre CAUBET, Mickael GROS-JEAN
  • Patent number: 9000596
    Abstract: A MOS transistor having a gate insulator including a dielectric of high permittivity and a conductive layer including a TiN layer, wherein the nitrogen composition in the TiN layer is sub-stoichiometric in its lower portion and progressively increases to a stoichiometric composition in its upper portion.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: April 7, 2015
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Pierre Caubet, Sylvain Baudot
  • Publication number: 20140319616
    Abstract: At least one MOS transistor is produced by forming a dielectric region above a substrate and forming a gate over the dielectric region. The gate is formed to include a metal gate region. Formation of the metal gate region includes: forming a layer of a first material configured to reduce an absolute value of a threshold voltage of the transistor, and configuring a part of the metal gate region so as also to form a diffusion barrier above the layer of the first material. Then, doped source and drain regions are formed using a dopant activation anneal.
    Type: Application
    Filed: April 17, 2014
    Publication date: October 30, 2014
    Applicant: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Sylvain Baudot, Pierre Caubet, Florian Domengie
  • Publication number: 20140097504
    Abstract: A method for forming an aluminum titanium nitride layer on a wafer by plasma-enhanced physical vapor deposition including a first step at a radio frequency power ranging between 100 and 500 W only, and a second step at a radio frequency power ranging between 500 and 1,000 W superimposed to a D.C. power ranging between 500 and 1,000 W. An insulated gate comprising such an aluminum titanium nitride layer.
    Type: Application
    Filed: September 20, 2013
    Publication date: April 10, 2014
    Inventors: Pierre CAUBET, Florian DOMENGIE, Sylvain BAUDOT
  • Publication number: 20130001708
    Abstract: A MOS transistor having a gate insulator including a dielectric of high permittivity and a conductive layer including a TiN layer, wherein the nitrogen composition in the TiN layer is sub-stoichiometric in its lower portion and progressively increases to a stoichiometric composition in its upper portion.
    Type: Application
    Filed: June 22, 2012
    Publication date: January 3, 2013
    Inventors: Pierre Caubet, Sylvain Baudot
  • Patent number: 8053871
    Abstract: A metal barrier is realized on top of a metal portion of a semiconductor product, by forming a metal layer on the surface of the metal portion, with this metal layer comprising a cobalt-based metal material. Then, after an optional deoxidation step, a silicidation step and a nitridation step of the cobalt-based metal material of the metal layer are performed. The antidiffusion properties of copper atoms (for example) and the antioxidation properties of the metal barrier are improved.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: November 8, 2011
    Assignee: STMicroelectronics S.A.
    Inventors: Pierre Caubet, Laurin Dumas, Cecile Jenny
  • Patent number: 8018062
    Abstract: A semiconductor product includes a portion made of copper, a portion made of a dielectric and a self-aligned barrier between the copper portion and the dielectric portion. The self-aligned barrier includes a first copper silicide layer comprising predominantly first copper silicide molecules, and a second copper silicide layer comprising predominantly second copper silicide molecules. The proportion of the number of silicon atoms is higher in the second silicide molecules than in the first silicide molecules. The second copper silicide layer is positioned between the copper portion and the first copper silicide layer. A nitride layer may overlie at least part of the first copper silicide layer.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: September 13, 2011
    Assignee: STMicroelectronics S.A.
    Inventors: Pierre Caubet, Nicolas Casanova
  • Patent number: 8013284
    Abstract: An integrated circuit includes at least one photosensitive element capable of delivering an electrical signal when light of at least one wavelength of the visible spectrum reaches it, and an electrooptic system functioning as an electrochemical shutter. The electrooptic system is located in the path of at least one light ray capable of reaching the photosensitive element and possesses at least one optical property, dependent on electrochemical reaction, that can be modified by an electrical control signal. The optical property is preferably transmission.
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: September 6, 2011
    Assignee: STMicroelectronics S.A.
    Inventors: Pierre Caubet, Michael Gros-Jean
  • Patent number: 7851915
    Abstract: An electronic component comprising several superimposed layers of materials including a TiCN barrier layer. A process for depositing a TiCN layer in order to obtain an electronic component, where a titanium precursor is chosen from among tetrakis(dimethylamido)titanium and/or tetrakis(diethylamido)titanium and is decomposed on a substrate by plasma-enhanced atomic layer deposition (PEALD) where the plasma is obtained with a hydrogen-rich gas which can contain nitrogen with at most 5 atomic % nitrogen and at least 95 atomic % hydrogen.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: December 14, 2010
    Assignee: STMicroelectronics S.A.
    Inventors: Pierre Caubet, Rym Benaboud