Abstract: A read/write memory cell comprises a first switch having one input which constitutes the data input-output of the cell and another input connected to a loop circuit comprises a first inverter, a second inverter and a second switch. The first and second switches are controlled in such a way that on a write operation the first is closed and the second open. In the absence of any write or read operation the first switch is open and the second switch is closed. On a read operation both switches are closed. A read/write memory of N words each of P bits is obtained by associating N.times.P cells of this kind in a matrix comprising N rows and P columns.

Abstract: A prediffused integrated circuit having rows of basic cells on a substrate. Each basic cell includes two MOS transistors connected in series through a common drain or source electrode, each transistor having a separate gate. All basic cells in a row are the same type while adjacent rows alternate between p-type and n-type.

Abstract: A switching system for telephone exchanges employing pulse code modulation (PCM). The time division switching network uses standard circuits of a single type, i.e., symmetrical time division matrices (MTS) and, in a particular embodiment, one PCM telephone junction is multipled onto two inputs of two MTSs and the latter are rejoined by two bi-directional junctions so that the construction of telephone exchange according to the invention permits simple and easy extensions of the capacity of the switching system.

Abstract: A switching network with k=p+q inputs and as many outputs comprises one or more symmetrical time-division matrices, k being eight or a multiple of eight in the embodiments specifically disclosed. A larger number p of incoming subscriber links and a smaller number q of exchange outputs are respectively connected to p outgoing subscriber links and q exchange inputs. Digitized voice samples arriving over each incoming link in successive time slots of a recurrent frame, allocated to respective subscribers, are stored in each matrix and are selectively distributed to the reduced number of time slots sent to the exchange under the control of switching instructions from the exchange; conversely, signal samples received from the exchange in successive time slots are distributed to selected time slots of outgoing links. Signal paths can also be established between network inputs and outputs connected to incoming and outgoing links, thereby enabling direct communication between subscribers served by the network.

Abstract: The invention relates to the connection networks used for switching digital signals, more especially telephonic PCM signals. It consists in organizing the spatial stage of a network of the TST type operating in series mode so as to divide into two the number of switching planes of that network. Each plane is with blocking although the assembly is without blocking. Moreover the number of time paths that enables the spatial stage to be traversed is doubled.

Abstract: The invention relates to switching matrices used in exchanges of time-division kind and to networks using that kind of matrices. It consists in utilizing at the input and output of a symmetrical time matrix, a multiplexer and a demultiplexer which enable the overall circuit to address an arbitrary IT (time slot) of an arbitrary incoming junction, to an arbitrary IT on an arbitrary outgoing junction. A network using only that kind of matrices is disclosed.

Abstract: The invention relates to time-division exchanges in which the connection between the subscribers is established successively in time at the same frequency as a sampling of telephone signals. It consists in carrying out the spatial multiplex switching stage simultaneously on k words in series mode, each word using a separate spatial multiplex switch. A spatial multiplex switching stage with k independent elements is thus provided.This invention relates to time-division exchanges, in which the connection between the subscribers is established successively in time at the same rate as a sampling of telephone signals. The invention also relates to methods reshaping an exchange of this kind.These signals are generally sampled at a frequency of 8kc/s, after which the value of each sample is coded by a number of 8 bits.

Abstract: The invention relates to time-division exchanges in which the connection between the subscribers is established successively in time at the same rate as a sampling of telephone signals. It consists in offering to each subscriber circuit two incoming channels and two outgoing channels, the choice between which is made by a memory comprising an additional bit reserved for this choice.

Abstract: In an electronic switching system, there is provided an arrangement which, without doubling the computers of the control units, enables the switching elements of the system to be controlled without interruption in the event of a failure affecting their control. To this end, the system comprises n control units each with an independent store (memory). The program corresponding to two functions i.e. to the control of two groups of switching elements is written in the independent store of each unit. Exchange memories, interconnecting the independent stores in twos, enable the momentary data necessary for monitoring of the group of switching elements in charge of the control unit under failure to be transferred from this unit to the other unit holding, in its independent store, the program relating to the same group.

Abstract: A space division switching network having a plurality of stages is disclosed for use as part of a time-space-time division switching system. The network employs MOS technology with standard printed circuit boards enabling very compact assembly. To enable a maximum number of stages to be placed on a standard board with appropriate electrical connections to each stage over the standard number of terminals, addresses of crosspoints are supplied in parallel over common address conductors and the appropriate stage is then switched through an enable signal.

Abstract: A system is disclosed for checking and correcting the synchronism of bits stored in a circulating memory which is part of a PCM switching system. Periodically, bits previously written in an addressable memory are read-out and compared to corresponding bits supplied by the circulating memory. In accordance with results of the comparison, a synchronism signal or a fast or slow correction signal is supplied.