Patents by Inventor Pierre Dautriche
Pierre Dautriche has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11616516Abstract: According to one aspect, an embodiment radio frequency receiver device comprises an input interface configured to receive a radio frequency signal of a given type and convert same into an electric signal, a detector configured to detect at least one voltage level in the electric signal, a pulse generator configured to generate at least one pulse train representative of the voltage levels detected, and a processing unit configured to determine the type of the radio frequency signal from the at least one pulse train.Type: GrantFiled: May 25, 2022Date of Patent: March 28, 2023Assignee: STMICROELECTRONICS SAInventors: Pierre Dautriche, Sylvain Engels
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Publication number: 20220286149Abstract: According to one aspect, an embodiment radio frequency receiver device comprises an input interface configured to receive a radio frequency signal of a given type and convert same into an electric signal, a detector configured to detect at least one voltage level in the electric signal, a pulse generator configured to generate at least one pulse train representative of the voltage levels detected, and a processing unit configured to determine the type of the radio frequency signal from the at least one pulse train.Type: ApplicationFiled: May 25, 2022Publication date: September 8, 2022Inventors: Pierre Dautriche, Sylvain Engels
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Patent number: 11374597Abstract: According to one aspect, an embodiment radio frequency receiver device comprises an input interface configured to receive a radio frequency signal of a given type and convert same into an electric signal, a detector configured to detect at least one voltage level in the electric signal, a pulse generator configured to generate at least one pulse train representative of the voltage levels detected, and a processing unit configured to determine the type of the radio frequency signal from the at least one pulse train.Type: GrantFiled: May 24, 2021Date of Patent: June 28, 2022Assignee: STMICROELECTRONICS SAInventors: Pierre Dautriche, Sylvain Engels
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Publication number: 20210399749Abstract: According to one aspect, an embodiment radio frequency receiver device comprises an input interface configured to receive a radio frequency signal of a given type and convert same into an electric signal, a detector configured to detect at least one voltage level in the electric signal, a pulse generator configured to generate at least one pulse train representative of the voltage levels detected, and a processing unit configured to determine the type of the radio frequency signal from the at least one pulse train.Type: ApplicationFiled: May 24, 2021Publication date: December 23, 2021Inventors: Pierre Dautriche, Sylvain Engels
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Patent number: 10181654Abstract: A millimeter wave transceiver including a plate forming an interposer having its upper surface supporting an interconnection network and having its lower surface intended to be assembled on a printed circuit board by bumps; an integrated circuit chip assembled on the upper surface of the interposer; antennas made of tracks formed on the upper surface of the interposer; and reflectors on the upper surface of the printed circuit board in front of each of the antennas, the effective distance between each antenna and the reflector plate being on the order of one quarter of the wavelength, taking into account the dielectric constants of the interposed materials.Type: GrantFiled: September 29, 2015Date of Patent: January 15, 2019Assignee: STMicroelectronics SAInventors: Jean-Francois Carpentier, Sébastien Pruvost, Patrice Garcia, Pierre Busson, Pierre Dautriche
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Publication number: 20170271777Abstract: A connector for a plastic waveguide includes a connector body having first and second openings aligned with one another. The first opening is configured to receive the plastic waveguide. A radio frequency (RF) antenna is positioned within the second opening of the connector body.Type: ApplicationFiled: June 5, 2017Publication date: September 21, 2017Inventors: Baudouin Martineau, Olivier Richard, Didier Belot, Pierre Dautriche
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Patent number: 9647625Abstract: A method for manufacturing a wafer on which are formed resonators, each resonator including, above a semiconductor substrate, a stack of layers including, in the following order from the substrate surface: a Bragg mirror; a compensation layer made of a material having a temperature coefficient of the acoustic velocity of a sign opposite to that of all the other stack layers; and a piezoelectric resonator, the method including the successive steps of: a) depositing the compensation layer; and b) decreasing thickness inequalities of the compensation layer due to the deposition method, so that this layer has a same thickness to within better than 2%, and preferably to within better than 1%, at the level of each resonator.Type: GrantFiled: November 19, 2013Date of Patent: May 9, 2017Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SASInventors: David Petit, Sylvain Joblot, Pierre Bar, Jean-Francois Carpentier, Pierre Dautriche
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Patent number: 9257754Abstract: A millimeter wave transceiver including a plate forming an interposer having its upper surface supporting an interconnection network and having its lower surface intended to be assembled on a printed circuit board by bumps; an integrated circuit chip assembled on the upper surface of the interposer; antennas made of tracks formed on the upper surface of the interposer; and reflectors on the upper surface of the printed circuit board in front of each of the antennas, the effective distance between each antenna and the reflector plate being on the order of one quarter of the wavelength, taking into account the dielectric constants of the interposed materials.Type: GrantFiled: December 20, 2011Date of Patent: February 9, 2016Assignee: STMicroelectronics SAInventors: Jean-Francois Carpentier, Sebastien Pruvost, Patrice Garcia, Pierre Busson, Pierre Dautriche
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Publication number: 20160020524Abstract: A millimeter wave transceiver including a plate forming an interposer having its upper surface supporting an interconnection network and having its lower surface intended to be assembled on a printed circuit board by bumps; an integrated circuit chip assembled on the upper surface of the interposer; antennas made of tracks formed on the upper surface of the interposer; and reflectors on the upper surface of the printed circuit board in front of each of the antennas, the effective distance between each antenna and the reflector plate being on the order of one quarter of the wavelength, taking into account the dielectric constants of the interposed materials.Type: ApplicationFiled: September 29, 2015Publication date: January 21, 2016Inventors: Jean-Francois Carpentier, Sébastien Pruvost, Patrice Garcia, Pierre Busson, Pierre Dautriche
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Publication number: 20150372388Abstract: A connector for a plastic waveguide includes a connector body having first and second openings aligned with one another. The first opening is configured to receive the plastic waveguide. A radio frequency (RF) antenna is positioned within the second opening of the connector body.Type: ApplicationFiled: June 1, 2015Publication date: December 24, 2015Inventors: Baudouin MARTINEAU, Olivier RICHARD, Didier BELOT, Pierre DAUTRICHE
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Patent number: 8981817Abstract: A circuit having a centralized PT compensation circuit to provide compensation signals to localized I/O blocks on the chip. Process variations and temperature variations tend to be approximately uniform across an integrated circuit chip. Thus, a single, centralized PT compensation circuit may be used instead of one PT compensation circuit per I/O section as with solutions of the past. Further, the PT compensation circuit may generate a digital code indicative of the effects of process and temperature. Further yet, each section of I/O block may have a local voltage compensation circuit to compensate the voltage variation of the I/O block. The voltage compensation circuit utilizes an independent reference voltage. The reference voltage is generated by the PT compensation circuit, which is placed centrally in the IC chip and hence any need to repeat the reference generation for each I/O block is eliminated.Type: GrantFiled: June 25, 2013Date of Patent: March 17, 2015Assignees: STMicroelectronics International N.V., STMicroelectronics (Crolles 2) SASInventors: Vinod Kumar, Pradeep Kumar Badrathwal, Saiyid Mohammad Irshad Rizvi, Paras Garg, Kallol Chatterjee, Pierre Dautriche
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Patent number: 8957457Abstract: A method for manufacturing a semiconductor chip stack device is provided. The method includes forming a first connecting element array on a surface of a first semiconductor chip; forming a second connecting element array on a surface of a second semiconductor chip, the second array comprising more connecting elements than the first array and the pitch of the first array being a multiple of the pitch of the second array; applying the first chip against the second chip; and setting up test signals between the first and second chips to determine the matching between the connecting elements of the first array and the connecting elements of the second array.Type: GrantFiled: November 22, 2011Date of Patent: February 17, 2015Assignee: STMicroelectronics SAInventors: Richard Fournel, Pierre Dautriche
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Patent number: 8933737Abstract: A variable frequency clock generator. In aspects, a clock generator includes a droop detector circuit configured to monitor a voltage supply to an integrated circuit. If the supply voltage falls below a specific threshold, a droop voltage flag may be set such that a frequency-locked loop is triggered into a droop voltage mode for handling the voltage droop at the supply voltage. In response, a current control signal that is input to an oscillator that generates a system clock signal is reduced by sinking current away from the current control signal to the oscillator. This results in an immediate reduction on the system clock frequency. Such a state remains until the voltage droop has dissipated when the current path is removed for sinking some of the current.Type: GrantFiled: October 4, 2013Date of Patent: January 13, 2015Assignees: STMicroelectronics International N.V., STMicroelectronics (Crolles 2) SASInventors: Kallol Chatterjee, Nitin Agarwal, Junaid Yousuf, Nitin Gupta, Pierre Dautriche
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Publication number: 20150002197Abstract: A variable frequency clock generator. In aspects, a clock generator includes a droop detector circuit configured to monitor a voltage supply to an integrated circuit. If the supply voltage falls below a specific threshold, a droop voltage flag may be set such that a frequency-locked loop is triggered into a droop voltage mode for handling the voltage droop at the supply voltage. In response, a current control signal that is input to an oscillator that generates a system clock signal is reduced by sinking current away from the current control signal to the oscillator. This results in an immediate reduction on the system clock frequency. Such a state remains until the voltage droop has dissipated when the current path is removed for sinking some of the current.Type: ApplicationFiled: October 4, 2013Publication date: January 1, 2015Applicants: STMicroelectronics International N.V., STMicroelectronics (CROLLES 2) SASInventors: Kallol CHATTERJEE, Nitin AGARWAL, Junaid YOUSUF, Nitin GUPTA, Pierre DAUTRICHE
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Publication number: 20140375357Abstract: A circuit having a centralized PT compensation circuit to provide compensation signals to localized I/O blocks on the chip. Process variations and temperature variations tend to be approximately uniform across an integrated circuit chip. Thus, a single, centralized PT compensation circuit may be used instead of one PT compensation circuit per I/O section as with solutions of the past. Further, the PT compensation circuit may generate a digital code indicative of the effects of process and temperature. Further yet, each section of I/O block may have a local voltage compensation circuit to compensate the voltage variation of the I/O block. The voltage compensation circuit utilizes an independent reference voltage. The reference voltage is generated by the PT compensation circuit, which is placed centrally in the IC chip and hence any need to repeat the reference generation for each I/O block is eliminated.Type: ApplicationFiled: June 25, 2013Publication date: December 25, 2014Inventors: Vinod KUMAR, Pradeep Kumar BADRATHWAL, Saiyid Mohammad Irshad RIZVI, Paras GARG, Kallol CHATTERJEE, Pierre DAUTRICHE
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Publication number: 20140075726Abstract: A method for manufacturing a wafer on which are formed resonators, each resonator including, above a semiconductor substrate, a stack of layers including, in the following order from the substrate surface: a Bragg mirror; a compensation layer made of a material having a temperature coefficient of the acoustic velocity of a sign opposite to that of all the other stack layers; and a piezoelectric resonator, the method including the successive steps of: a) depositing the compensation layer; and b) decreasing thickness inequalities of the compensation layer due to the deposition method, so that this layer has a same thickness to within better than 2%, and preferably to within better than 1%, at the level of each resonator.Type: ApplicationFiled: November 19, 2013Publication date: March 20, 2014Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SAInventors: David Petit, Sylvain Joblot, Pierre Bar, Jean-Francois Carpentier, Pierre Dautriche
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Publication number: 20120154238Abstract: A millimeter wave transceiver including a plate forming an interposer having its upper surface supporting an interconnection network and having its lower surface intended to be assembled on a printed circuit board by bumps; an integrated circuit chip assembled on the upper surface of the interposer; antennas made of tracks formed on the upper surface of the interposer; and reflectors on the upper surface of the printed circuit board in front of each of the antennas, the effective distance between each antenna and the reflector plate being on the order of one quarter of the wavelength, taking into account the dielectric constants of the interposed materials.Type: ApplicationFiled: December 20, 2011Publication date: June 21, 2012Applicant: STMicroelectronics SAInventors: Jean-Francois Carpentier, Sebastien Pruvost, Patrice Garcia, Pierre Busson, Pierre Dautriche
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Publication number: 20120126230Abstract: A method for manufacturing a semiconductor chip stack device is provided. The method includes forming a first connecting element array on a surface of a first semiconductor chip; forming a second connecting element array on a surface of a second semiconductor chip, the second array comprising more connecting elements than the first array and the pitch of the first array being a multiple of the pitch of the second array; applying the first chip against the second chip; and setting up test signals between the first and second chips to determine the matching between the connecting elements of the first array and the connecting elements of the second array.Type: ApplicationFiled: November 22, 2011Publication date: May 24, 2012Applicant: STMicroelectronics SAInventors: Richard Fournel, Pierre Dautriche
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Publication number: 20110080233Abstract: A method for manufacturing a wafer on which are formed resonators, each resonator including, above a semiconductor substrate, a stack of layers including, in the following order from the substrate surface: a Bragg mirror; a compensation layer made of a material having a temperature coefficient of the acoustic velocity of a sign opposite to that of all the other stack layers; and a piezoelectric resonator, the method including the successive steps of: a) depositing the compensation layer; and b) decreasing thickness inequalities of the compensation layer due to the deposition method, so that this layer has a same thickness to within better than 2%, and preferably to within better than 1%, at the level of each resonator.Type: ApplicationFiled: October 1, 2010Publication date: April 7, 2011Applicants: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SASInventors: David Petit, Sylvain Joblot, Pierre Bar, Jean-Francois Carpentier, Pierre Dautriche
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Patent number: 6304113Abstract: A device for synchronizing a reference event of an analog signal, which includes an analog-to-digital converter receiving an input signal, a register receiving the converter output, a phase-locked loop including an oscillator generating several phase-shifted clock signals of same period, a first clock signal clocking the register, a multiplexer receiving the other clock signals on respective inputs, the output of which clocks said converter, and an analysis circuit connected to control the multiplexer according to successive values of the register output.Type: GrantFiled: July 28, 2000Date of Patent: October 16, 2001Assignee: STMicroelectronics S.A.Inventor: Pierre Dautriche