Abstract: Technology is disclosed related to methods and devices for reducing the top-level placement and routing runtime of a field-programmable gate arrays (FPGA). The method can comprise: generating a global signal netlist comprising feedthrough connections through non-adjacent FPGA modules; selecting a predefined signal connection pattern for the global signal netlist; generating pre-routed feedthrough connections based on the predefined signal connection pattern and the global signal netlist; and generating a pre-routed global signal netlist from the pre-routed feedthrough connections. The FPGA can comprise an FPGA module configured to send a pre-routed global signal to a non-adjacent FPGA module through a pre-routed feedthrough connection identified using a predefined signal connection pattern.

Abstract: Techniques for implementing a multi-branch neural network in an edge network are disclosed, where the multi-branch neural network is configured to infer latent features from fused sensor time series exogenous inputs. A multi-branch neural network is configured to include a LSTM branch and two FC branches. The multi-branch neural network is deployed on an edge node, which receives raw input from sensors. The raw input is fed into the LSTM branch and into the second FC branch. The raw input is fed into a normalization block that performs feature-wise normalization to generate normalized input. The normalized input is fed into the first FC block. The multi-branch neural network is used to generate a latent inference based on outputs provided by the LSTM branch and the two FC branches.

Abstract: Electronic devices and methods for single event effect mitigation are described. The device can include a processor, a memory cell, and an integrated particle sensor. The memory cell can comprise a substrate, a deep well coupled to the substrate, and a ground-coupled well coupled to the deep well. The integrated particle sensor can be coupled between the substrate and the deep well, and the ground-coupled well and the deep well. The integrated particle sensor can be operable to detect an ionizing particle generating the single event effect. The electronic device can be a field-programmable gate array. The method can include detecting an ionizing particle generating a single event effect at a memory cell of the electronic device, switching from the memory cell to a redundant memory cell associated with the memory cell when the single event effect is detected, and reconfiguring the memory cell based on the redundant memory cell.

Abstract: One embodiment provides a resistive random-access memory (RRAM) based convolutional block including a complementary pair of RRAMs having a first RRAM and a second RRAM, a programming circuit coupled to the complementary pair of RRAMs, and a XNOR sense amplifier circuit coupled to the complementary pair of RRAMs. The programming circuit is configured to receive a kernel bit from a kernel matrix, program the first RRAM to at least one selected from a group consisting of a low resistive state (LRS) and a high resistive state (HRS) based on the kernel bit, and program the second RRAM to other of the LRS and the HRS. The XNOR sense amplifier circuit is configured to receive an input bit from an input matrix, perform a XNOR operation between the input bit and the kernel bit read from the complementary pair of RRAMs, and output a XNOR output based on the XNOR operation.

Abstract: A computer system for recursive calibration of a sensor network receives a first data communication from a first sensor node that is a neighbor to a calibrated sensor node. The computer system then updates a set of linear regressions between the first sensor node and a set of neighboring sensor nodes, which include the neighboring, calibrated sensor node. The computer system calibrates the first sensor node using an average of the set of linear regressions weighted by a correlation. When the first sensor node is calibrated, the computer system uses the calibrated first sensor node in calibration of a neighboring, uncalibrated sensor node. The computer system then gathers, at the first sensor node, a calibrated sensor reading.

Abstract: A computer system for recursive calibration of a sensor network receives a first data communication from a first sensor node that is a neighbor to a calibrated sensor node. The computer system then updates a set of linear regressions between the first sensor node and a set of neighboring sensor nodes, which include the neighboring, calibrated sensor node. The computer system calibrates the first sensor node using an average of the set of linear regressions weighted by a correlation. When the first sensor node is calibrated, the computer system uses the calibrated first sensor node in calibration of a neighboring, uncalibrated sensor node. The computer system then gathers, at the first sensor node, a calibrated sensor reading.

Abstract: One embodiment provides a resistive random-access memory (RRAM) based convolutional block including a complementary pair of RRAMs having a first RRAM and a second RRAM, a programming circuit coupled to the complementary pair of RRAMs, and a XNOR sense amplifier circuit coupled to the complementary pair of RRAMs. The programming circuit is configured to receive a kernel bit from a kernel matrix, program the first RRAM to at least one selected from a group consisting of a low resistive state (LRS) and a high resistive state (HRS) based on the kernel bit, and program the second RRAM to other of the LRS and the HRS. The XNOR sense amplifier circuit is configured to receive an input bit from an input matrix, perform a XNOR operation between the input bit and the kernel bit read from the complementary pair of RRAMs, and output a XNOR output based on the XNOR operation.

Abstract: A Field Programmable Gate Array (FPGA) of the island-type comprising a plurality of cluster-based Configurable Logic Blocks (CLBs), whereby each of the cluster-based CLBs is surrounded by a global routing structure formed by a plurality of multiplexers and pass/transmission-gates organized in Switch Boxes (SBs) and Connection Blocks (CBs), the switch boxes and the connection blocks comprising at least a first plurality of resistive memories inserted in a data path of a first routing architecture of the switch boxes and the connection blocks. Each CLB contains Basic Logic Elements (BLEs), as well as local routing resources.

Abstract: A Field Programmable Gate Array (FPGA) of the island-type comprising a plurality of cluster-based Configurable Logic Blocks (CLBs), whereby each of the cluster-based CLBs is surrounded by a global routing structure formed by a plurality of multiplexers and pass/transmission-gates organized in Switch Boxes (SBs) and Connection Blocks (CBs), the switch boxes and the connection blocks comprising at least a first plurality of resistive memories inserted in a data path of a first routing architecture of the switch boxes and the connection blocks. Each CLB contains Basic Logic Elements (BLEs), as well as local routing resources.

Abstract: The present invention is a non-volatile memory cell containing at least two distinct memory zones, each formed in a resistivity-change material, the memory cell containing at least one heating element for each memory zone, each heating element having at least two ends, one of which is connected to a supply line and the other of which is brought into contact with the resistivity-change material, characterized in that the resistivity-change material is arranged in a single block common to each of the memory zones of the memory cell, so as to create distinct memory zones locally.

Abstract: The object of the present invention is a non-volatile memory cell (10) containing at least two distinct memory zones (17), each formed in a resistivity-change material (14), the memory cell (10) containing at least one heating element (16) for each memory zone (17), each heating element (16) having at least two ends, one of which is connected to a supply line (V1, V2, . . . , VN) and the other of which is brought into contact with the resistivity-change material (14), characterized in that the resistivity-change material (14) is arranged in a single block (34) common to each of the memory zones (17) of the memory cell (10), so as to create distinct memory zones (17) locally.