Abstract: An adsorption refrigeration device comprising an evaporator chamber containing a refrigerant liquid that evaporates under the effect of a depression, a connecting device and an adsorption chamber containing an adsorbent capable of fixing the vapors of the refrigerant liquid, wherein the adsorbent is constituted by one or more rigid blocks comprising a plurality of cavities, at least one part of said cavities being feeder cavities capable of diffusing vapors of refrigerant liquid on the adsorbent.

Abstract: The invention relates to a method for manufacturing a self-refrigerating drinks package, characterised in that it includes a step consisting in assembling refrigeration means inside the package, said refrigeration means being composed of a cavity containing a refrigerating liquid able to evaporate under the effect of a negative pressure, means of connecting said cavity to external pumping means by adsorption being provided in the package, partial pressure of the non-adsorbable gases in the internal cavity being maintained below 3 millibar.

Abstract: A self-cooling package for beverages, comprises cooling means internal to said package and means of connection to pumping means external to said package, the internal cooling means being formed by a cavity filled with a refrigerant liquid that evaporates under the effect of a depression.

Abstract: A self-cooling package for beverages that includes a cooling device internal to the package and connection to a pumping device external to the package. The internal cooling device is by a cavity filled with a coolant that evaporates under the effect of a depression.

Abstract: Automatic identification system for objects or persons by remote interrogation. The invention relates to an interrogating E/R (emitter/receiver) or gate associated with an answering E/R or tag having a digitized code identifying the same. The gate supplies four information types in the form of signals to the tags which answer "yes" or, by an absence of any answer, "no" until the gate has found their codes. When its code has been found, the tag is inhibited, thus permitting the detection of other codes. The invention more particularly applies to the monitoring of persons carrying answering E/Rs or to the billing of goods on sale in a large surface area.

Abstract: The device has at least one planar detector (2.sub.a, 2.sub.b) able to transform a radiation (8) into electrical charges and a common electrode (12) on an input face and a mosaic of point electrodes (14) and metal bands (34.sub.a -34.sub.e) on an output face, several planar integrated circuit chips (10a, 10b) facing the input face of the detector and having a mosaic of reading circuits (16) and metal bands (30a, 30d) for connecting the circuits to external supply, control and processing devices for output signals, each reading circuit being hybridized by a microsphere to a point electrode and the bands of the chip being positioned facing bands of the detector and hybridized thereto by microspheres. The device is to be used in mamography or dental imaging.

Abstract: A non-volatile storage cell has (a) storage points which are insulated from one another and each having a stack of gates formed, in order, by a first insulant in contact with the substrate, a floating gate, a second insulant and a control gate, a source and a drain formed in substrate on either side of the stack and a channel, whose length is oriented in a direction (x) and (b) conductor lines serving to apply electric signals to the stacks of gates and the drains, the second insulant having, in a plane perpendicular to the surface of the substrate and containing the first direction (x), the shape of an inverted U within which is located the entire floating gate, the control gate also being shaped like an inverted U, without projection and within which is located the entire second insulant.

Abstract: The invention concerns the method to produce an EPROM or EEPROM type integrated memory cell on a semiconductor substrate. The cell comprises memory points, electrically insulated from each other, each memory point comprising a source (4), a drain (6), a floating gate (350), a control grid (38), a channel (5) situated under the floating gate (350), the source (4) and the drain (6) being situated on both sides of the floating (350), the floating gates of each memory point being laterally distant and insulated along a first direction (X) from one or two other floating gates, the production of the cell comprising a stage for embodying lateral insulations (320) of the floating gates along the first direction (X), then a stage for embodying the actual floating gates (350), which makes it possible to obtain insulations between submicronic floating gates.Application for the embodiment of integrated memory cells.

Abstract: A process for the production of a MIS transistor with a rising substrate/gate dielectric interface wall wherein on the surface of a semiconductor substrate having a given doping type is formed a first electrically insulating layer surrounding a zone of the substrate surface. On the first insulating layer and on said zone is formed a second layer. Part of that zone is made to appear by eliminating a fragment of the second layer, which fragment extends above that part, which thus constitutes the bottom of a hole made in the second layer and above part of the first insulating layer. A cavity is formed having at least one rising wall in the bottom of the hole. A third electrically insulating layer is formed on the surface of the aforesaid zone part. On the thus treated surface is formed an electrically conductive layer which eliminated, except in a zone corresponding to the fragment, so as to obtain a transistor gate.

Abstract: The CMOS circuit has n regions (20a) and p regions (32a) formed in a silicon substrate (2). A first mask is produced on the substrate, whose patterns (10a) mask the p regions (32a). A second mask (22a) is formed on the substrate masking the n regions (20a). The first mask, whose sides have in their upper part an inclined profile, can be selectively etched with respect to the second mask. The patterns of the first and second masks are separate and fix between them the location and width of the isolation trenches (24). The trenches are formed by etching the substrate and simultaneous etching takes place of the first mask and the substrate for forming in the upper part (24a) of each trench and in contact with the p regions, sides (26) inclined with respect to the upper surface of the substrate, so that the section of the trenches (24) widens towards said upper substrate surface.

Abstract: The CMOS circuit has n regions (12a) and p regions (28) formed in a silicon substrate (2b). First and second masks are produced on substrate (2b), respectively having first (8a) and second (15) patterns masking the p regions and n regions. These masks can be selectively etched. The first and second patterns define between them the location of the isolation trenches (18) to be produced. The substrate is etched through the masks to form the trenches and simultaneously etching takes place of the first patterns and the underlying substrate in order to form in the upper part of the trenches inclined sides in contact with the p regions, in such a way that the section of trench (18) widens towards the upper surface of the substrate.

Abstract: A process for producing a memory cell, particularly of the ROM or EPROM type, having a matrix of memory points, each memory point comprising a source, a drain and at least one gate. In a first step, a mask is produced for defining the position of stacks in which the gates are produced. This is followed by the production of the sources and the drains during second and third successive and independent steps. The second step consists of an etching operation, a doping operation and an insulating operation, while the third step involves an etching operation and a doping operation. The operation is completed by producing the conductive lines connecting the drains of the memory points aligned in a direction Y.

Abstract: An a MIS integrated circuit, such as an EPROM memory cell integrated onto a semiconductor substrate comprises (a) memory points which are insulated from one another and have in each case a stack of materials formed from a first insulant in contact with the substrate, first and second gates separated from one another by a second insulant, the first gate being in contact with the first insulant, a source and a drain formed in the substrate on either side of the stack of gates, and a channel, whose length is oriented according to a first direction Y, (b) first metal lines parallel to the first direction for applying electric signals to said stacks and (c) second conductor lines parallel to a second direction X perpendicular to the first direction and produced on the drains for applying electric signals to said drains. A process for making the circuit is also disclosed.

Abstract: CMOS integrated circuit and process for the production of electric isolation zones in the integrated circuit.According to the invention the process comprises the following stages: formation of several trenches in a silicon substrate, thermal oxidation of the substrate leading to the formation of an oxide film on the sides and bottom of the trenches, elimination of the oxide film near the bottom of the trenches and filling the trenches with a conductive material, thus constituting an electrode connected to the substrate corresponding to the circuit earth.

Abstract: A process for the production of a MIS-type integrated circuit is disclosed.

Abstract: The storage cell comprises a bistable element formed from two channel P MOS transistors called first and second transistors, and two channel N MOS transistors, called third and fourth transistors, a fifth and a sixth channel N MOS transistor being used for controlling the bistable element, the different transistors of the cell being electrically interconnected in such a way that the interconnection lines used for connecting them do not cross.

Abstract: A method for interconnecting the active zones and/or gates of CMOS integrated circuits. The method comprises, during the formation of the gates in a first conductive coating, defining in the latter the dimensions of the connections to be produced, and wherein following the formation of the active zones, the gates are laterally insulated and then a second conductive coating producing the desired connections is deposited on the complete circuit, with the exception of the lateral insulation.

Abstract: A device for checking the mobile electrical charges in a MOS integrated circuit having a wafer support, a polarization means applying a potential difference between the two faces of the silicon wafer on which are formed the integrated circuits by means of two electrodes, one constituted by a conductive diaphragm covering the silicon wafer and which is kept in contact with the silicon wafer by a pressure difference between these two faces, while the other is constituted by the electrically conductive wafer support.

Abstract: A method for interconnecting the active zones and/or the gates of a C/MOS integrated circuit characterized in that, after producing the constituent elements of the integrated circuit with the exception of the connections, on the complete circuit is directly deposited a coating of a conductive material, which is then etched in order to form the desired connection.

Abstract: The invention relates to a process for the positioning of an interconnection line on an electric contact hole in an integrated circuit. According to the invention, one or more conductive layers forming a conductive covering are deposited on the complete integrated circuit. The first conductive layer is deposited by an isotropic process. The interconnection line to be produced is then masked by a resin layer, followed by the successive etching of each conductive layer. Finally, an overetching of these conductive layers is effected in the electric contact hole, followed by the elimination of the resin.