Abstract: The invention relates to data processing systems which make use of an addressable memory. It proposes a method and a system of operation which permits one to particularize or mark for future reference, as desired, certain addresses in the addressable memory by the creation of indicators associated with the particular addresses. These indicators are activated each time one of the particular addresses is called and the system is informed that it has just called up one of the addresses having an associated indicator. The indicators are locations which access subroutines.

Abstract: A data processing method of operation and system uses a processor, an addressable data memory, and an addressable data extension read-write memory. As a data word is written into and read out of the data memory, a data extension associated with the data word may be simultaneously respectively written into and read out of the extension memory. The extension supplements the data word to effectively double the length of the data word. An address bus and control bus cause the simultaneous inputting/outputting of data and extensions to and from the data memory and extension memory respectively. An intermediate storage means is used for inputting and outputting extensions to and from the extension memory. The intermediate storage means includes an interface adapter which interfaces the extension memory to the processor as though the extension memory is a peripheral I/O device. An INTERRUPT is used to alert the processor of the reading of an extended data word.

Abstract: The invention relates to data processing systems making use of an addressable memory. It proposes a process and system permitting qualifying terms to be associated with the data contained in the data memory by writing these qualifying terms at locations associated with the data within a qualifier and set aside for this purpose. These qualifying terms are characteristics of the data or the processing undergone by the data. The qualifier memory, which is interfaced with the processor as though it was a peripheral I/O device, uses an INTERUPT to alert the processor of the occurrence of a call on data which has an associated qualifier.

Abstract: A microinstruction address is determined in response to the content of an mediately preceding microinstruction. A data processing apparatus contains a memory for storing microinstructions at addressable locations. Testing bits are loaded into a test register while a microinstruction read from the memory is loaded into a microinstruction register.

Abstract: A plurality of sub-clock signals are derived from a main clock signal sou by advancing a shift register and a counter with pulses from the main clock source. The shift register is selectively loaded with a desired combination of sub-clock bits in response to a predetermined number of main clock pulses being supplied to the counter. The sub-clock signals are derived from output terminals at different stages of the shift register. The state of the sub-clock signals can be selectively frozen by decoupling pulses from the main clock source to inputs of the counter and shift register.