Patents by Inventor Pieter Cornelis Nicolaas Scheurwater

Pieter Cornelis Nicolaas Scheurwater has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Reduced chip testing scheme at wafer level
    Patent number: 7218093
    Abstract: The present invention relates to production testing of semiconductor devices, more specifically to production testing of such devices at wafer level. A method according to the present invention comprises the steps of generating (20) quality test-data at a limited number of semiconductor devices on the wafer, deciding (24) based on the generated quality test-data whether other semiconductor devices on the wafer are to be tested, and based on the result of the deciding step, testing (28) or not testing (26) the other semiconductor devices on the wafer. A corresponding wafer prober is also described.
    Type: Grant
    Filed: August 4, 2003
    Date of Patent: May 15, 2007
    Assignee: NXP B.V.
    Inventors: Cornelis Oene Cirkel, Pieter Cornelis Nicolaas Scheurwater