Patents by Inventor Pieter Van Der Wolf
Pieter Van Der Wolf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9246826Abstract: The present invention discloses an integrated circuit arrangement (100) comprising a data communication network comprising a plurality of connections (300), a plurality of modules (110) coupled to the data communication network via at least one network interface (120), the network interface comprising a plurality of buffers; a remote service module (150) being coupled to the data communication network via a further network interface (140), wherein each of said modules (1 10) is arranged to provide its network interface (120) with a service request (200) for the remote service module (150), said network interface being arranged to extend said service request with a first identifier (204) for establishing a network connection (300) with a remote service module (150); and a circuit portion (350) comprising a plurality of buffers (142) between the at least one network interface (120) and the remote service module (150) for storing service requests (200) from the plurality of modules (110), said circuit portion coType: GrantFiled: November 11, 2009Date of Patent: January 26, 2016Assignee: Synopsys, Inc.Inventors: Tomas Henriksson, Martijn Coenen, Pieter Van Der Wolf, Elisabeth Francisca Maria Steffens
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Patent number: 8745335Abstract: Memory arbiter with latency guarantees for multiple ports. A method of controlling access to an electronic memory includes measuring a latency value indicative of a time difference between origination of an access request from a port of a plurality of ports and a response from the electronic memory. The method also includes calculating a difference between the latency value for the port and a target value associated with the port. The method further includes calculating a running sum of differences for the port covering each of a plurality of access requests. Further, the method includes determining a delta of a priority value for the port based on the running sum of differences. Moreover, the method includes prioritizing the access by the plurality of ports according to associated priority values.Type: GrantFiled: June 29, 2011Date of Patent: June 3, 2014Assignee: Synopsys, Inc.Inventors: Pieter Van Der Wolf, Marc Jeroen Geuzebroek, Johannes Boonstra
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Patent number: 8732409Abstract: A cache management policy is provided, comprising a method for writing back to a memory (104) a data element set (122) stored in a cache (110). The method reduces the time some items stay in the cache, and thereby improves the utilization of the cache for some applications, especially for video applications. The method comprises determining that each one of the multiple data elements has been updated through at least one write request; marking the data element set as a write-back candidate, in dependency on said determination; and writing the write-back candidate to the memory.Type: GrantFiled: November 16, 2009Date of Patent: May 20, 2014Assignee: Entropic Communications, Inc.Inventors: Pieter Van Der Wolf, Abraham Karel Riemens, Jan-Willem Van de Waerdt
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Publication number: 20130007386Abstract: Memory arbiter with latency guarantees for multiple ports. A method of controlling access to an electronic memory includes measuring a latency value indicative of a time difference between origination of an access request from a port of a plurality of ports and a response from the electronic memory. The method also includes calculating a difference between the latency value for the port and a target value associated with the port. The method further includes calculating a running sum of differences for the port covering each of a plurality of access requests. Further, the method includes determining a delta of a priority value for the port based on the running sum of differences. Moreover, the method includes prioritizing the access by the plurality of ports according to associated priority values.Type: ApplicationFiled: June 29, 2011Publication date: January 3, 2013Applicant: SYNOPSYS INC.Inventors: Pieter Van Der WOLF, Marc Jeroen Geuzebroek, Johannes Boonstra
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Publication number: 20120226826Abstract: The present invention discloses an integrated circuit arrangement (100) comprising a data communication network comprising a plurality of connections (300), a plurality of modules (110) coupled to the data communication network via at least one network interface (120), the network interface comprising a plurality of buffers; a remote service module (150) being coupled to the data communication network via a further network interface (140), wherein each of said modules (110) is arranged to provide its network interface (120) with a service request (200) for the remote service module (150), said network interface being arranged to extend said service request with a first identifier (204) for establishing a network connection (300) with a remote service module (150); and a circuit portion (350) comprising a plurality of buffers (142) between the at least one network interface (120) and the remote service module (150) for storing service requests (200) from the plurality of modules (110), said circuit portion comType: ApplicationFiled: November 11, 2009Publication date: September 6, 2012Applicant: SYNOPSYS, INC.Inventors: Tomas Henriksson, Martijn Coenen, Pieter Van Der Wolf, Elisabeth Francisca Maria Steffens
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Publication number: 20110246723Abstract: A cache management policy is provided, comprising a method for writing back to a memory (104) a data element set (122) stored in a cache (110). The method reduces the time some items stay in the cache, and thereby improves the utilization of the cache for some applications, especially for video applications. The method comprises determining that each one of the multiple data elements has been updated through at least one write request; marking the data element set as a write-back candidate, in dependency on said determination; and writing the write-back candidate to the memory.Type: ApplicationFiled: November 16, 2009Publication date: October 6, 2011Inventors: Pieter Van Der Wolf, Abraham Karel Riemens, Van De Waerdt Jan-Willem
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Publication number: 20110197038Abstract: The invention relates to a method of controlling access of a System-on-Chip to an off-chip memory, wherein the System-on-Chip comprises a plurality of agents which need access to the memory.Type: ApplicationFiled: September 14, 2010Publication date: August 11, 2011Applicant: NXP B.V.Inventors: Tomas HENRIKSSON, Pieter van der WOLF
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Patent number: 7870347Abstract: The disclosed data processing system comprises a memory means (SDRAM), a plurality of data processing means (IP) provided for accessing to said memory means (SDRAM), and a communication interface means coupled between said memory means (SDRAM) and said plurality of data processing means (IP), said communication interface means including a network of nodes (H 11, H 12, H2), each node comprising at least one slave port (s) for receiving a memory access request from a data processing means (IP) or from a previous node and at least one master port (m) for issuing a memory access request to a next node or to said memory means (SDRAM) in accordance with the memory access request received at said slave port (s), wherein said at least one slave port (s) is connected to a master port (m) of a previous node or to one of said data processing means (IP) and said at least one master port (m) is connected to a slave port (s) of a next node or to said memory means (SDRAM).Type: GrantFiled: August 19, 2004Date of Patent: January 11, 2011Assignee: Koninklijke Philips Electronics N.V.Inventors: Pieter Van Der Wolf, Josephus Theodorus Johannes Van Eijndhoven, Johannes Boonstra
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Patent number: 7706377Abstract: Video stream processing, such as processing that includes MPEG decoding an subsequent post-processing involves using signal processing circuitry (102, 106) to execute a first and a second video stream processing function. The first video stream processing function produces frame data of successive video frames in a temporally ordered output sequence of frames. The second video stream processing function uses the frame data in an ordered input sequence of frames that differs from the output sequence, for example because later P-frames are needed to decode B frames. The frame data is buffered between application of the first and second video processing function to the frame data. A first and a second. buffer memory (12, 106) are used. The first buffer memory (12) is coupled to the signal processing circuitry via a shareable channel (15) such as an external IC terminals, but the processing circuitry does not use the shareable channel (15) to access the second buffer memory (106).Type: GrantFiled: February 25, 2005Date of Patent: April 27, 2010Assignee: NXP B.V.Inventors: Pieter Van Der Wolf, Abraham Karel Riemens, Om Prakash Gangwal
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Patent number: 7653736Abstract: Aspects involve effectively separating communication hardware in a data processing system by introducing a communication device for each processor. By introducing this separation the processors can concentrate on performing their function-specific tasks, while the communication device provide the communication support for the respective processor. Accordingly, in certain embodiments, a data processing system is provided with a computation, a communication support and a communication network layer.Type: GrantFiled: December 5, 2002Date of Patent: January 26, 2010Assignee: NXP B.V.Inventors: Josephus Theodorus Johannes Van Eijndhoven, Evert-Jan Daniƫl Pol, Martijn Johan Rutten, Pieter Van Der Wolf, Om Prakash Gangwal
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Publication number: 20070165712Abstract: Video stream processing, such as processing that includes MPEG decoding an subsequent post-processing involves using signal processing circuitry (102, 106) to execute a first and a second video stream processing function. The first video stream processing function produces frame data of successive video frames in a temporally ordered output sequence of frames. The second video stream processing function uses the frame data in an ordered input sequence of frames that differs from the output sequence, for example because later P-frames are needed to decode B frames. The frame data is buffered between application of the first and second video processing function to the frame data. A first and a second. buffer memory (12, 106) are used. The first buffer memory (12) is coupled to the signal processing circuitry via a shareable channel (15) such as an external IC terminals, but the processing circuitry does not use the shareable channel (15) to access the second buffer memory (106).Type: ApplicationFiled: February 25, 2005Publication date: July 19, 2007Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventors: Pieter Van Der Wolf, Abraham Riemens, Om Gangwal
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Publication number: 20070028038Abstract: The disclosed data processing system comprises a memory means (SDRAM), a plurality of data processing means (IP) provided for accessing to said memory means (SDRAM), and a communication interface means coupled between said memory means (SDRAM) and said plurality of data processing means (IP), said communication interface means including a network of nodes (H 11, H 12, H2), each node comprising at least one slave port (s) for receiving a memory access request from a data processing means (IP) or from a previous node and at least one master port (m) for issuing a memory access request to a next node or to said memory means (SDRAM) in accordance with the memory access request received at said slave port (s), wherein said at least one slave port (s) is connected to a master port (m) of a previous node or to one of said data processing means (IP) and said at least one master port (m) is connected to a slave port (s) of a next node or to said memory means (SDRAM).Type: ApplicationFiled: August 19, 2004Publication date: February 1, 2007Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventors: Pieter Van Der Wolf, Josephus Van Eijdhoven, Johannes Boonstra
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Publication number: 20050021807Abstract: The invention is based on the idea to effectively separate communication hardware, e.g. busses and memory, and computation hardware, e.g. processors, in a data processing system by introducing a communication means for each processor. By introducing this separation the processors can concentrate on performing their function-specific tasks, while the communication means provide the communication support for the respective processor. Therefore, a data processing system is provided with a computation, a communication support and a communication network layer. The computation layer comprises a first and at least a second processor for processing a stream of data objects. The first processor passes a number of data objects from a stream to the second processor which can then process the data objects. The communication network layer includes a memory and a communication network for linking the first processor and the second processors with said memory.Type: ApplicationFiled: December 5, 2002Publication date: January 27, 2005Inventors: Joseph Theodorus Van Eijndhoven, Evert Pol, Martijn Rutten, Pieter van Der Wolf, Om Gangwal
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Publication number: 20040190622Abstract: Method and system for motion compensation in video image data, comprising a motion estimator (12) arranged for analysing motion in consecutive frames of the video image data and deriving a motion vector field in dependence on said motion, a motion compensator (14) connected to the motion estimator (12) and first storage means (15). The motion compensator (14) is arranged for performing motion compensation by storing a subset of the video image data in a first storage means (15) and, for each vector retrieving the required data from the first storage means (15), where in cases that the required data is not entirely available in the first storage means (15), video image data containing at least the missing parts of the required data, is retrieved from a second storage means (10) and stored in the first storage means (15).Type: ApplicationFiled: December 22, 2003Publication date: September 30, 2004Inventors: Robert Schutten, Abraham Riemens, Pieter Van Der Wolf
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Publication number: 20040193693Abstract: A data processing apparatus according to the invention comprises at least a first (1.2) and a second processor (1.3), which processors are capable of communicating data to each other by exchanging tokens via a buffer according to a synchronization protocol. The protocol maintains synchronization information comprising at least a first and a second synchronization counter (writec, readc), which are readable by both processors. At least the first processor (1.2) is capable of modifying the first counter (writec), and at least the second processor (1.3) is capable of modifying the second counter (readc). The protocol comprises at least a first command (claim) which when issued by a processor results in a verification whether a requested number of tokens is available to said processor, and a second command (release) which results in updating one of the synchronization counters to indicate that tokens are released for use by the other processor. At least one of the processors (1.Type: ApplicationFiled: December 23, 2003Publication date: September 30, 2004Inventors: Om Prakash Gangwal, Pieter Van Der Wolf, Andre Krijn Nieuwland, Gerben Essink
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Patent number: 6415377Abstract: The data processor contains a memory and a data prefetch unit. The data prefetch unit contains a respective FIFO queue for storing prefetched data from each of a number of address streams respectively. The data prefetch unit uses programmable information to generate addresses from a plurality of address streams and prefetches data from addresses successively addressed by a present address for the data stream in response to progress of execution of a program by the processor. The processor has an instruction which causes the data prefetch unit to extract an oldest data from the FIFO queue for an address stream and which causes the data processor to use the oldest data in the manner of operand data of the instruction.Type: GrantFiled: June 3, 1999Date of Patent: July 2, 2002Assignee: Koninklijke Philips Electronics N.V.Inventors: Pieter Van Der Wolf, Kornelis A. Vissers
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Patent number: 6226715Abstract: The processing circuit contains a cache management unit which keeps information about a stream of addresses among addresses accessed by the processor. The cache management unit updates a current address for the stream in response to progress of execution of the program. The cache management unit is make selected storage locations in the cache memory available for reuse, a storage location in the cache memory which is in use for the data corresponding to the particular address being made available for reuse dependent on a position of the particular address relative to the current address.Type: GrantFiled: May 6, 1999Date of Patent: May 1, 2001Assignee: U.S. Philips CorporationInventors: Pieter Van Der Wolf, Pieter Struik