Patents by Inventor Pietro Fichera

Pietro Fichera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Protection of a power transistor
    Patent number: 7460349
    Abstract: A method and a circuit for protecting a transistor that controls the supply of an at least partially inductive load, including lowering the demagnetization voltage of the inductive load with respect to a demagnetization voltage set by a break-over component connected between a conduction terminal and the control terminal of the transistor.
    Type: Grant
    Filed: October 27, 2005
    Date of Patent: December 2, 2008
    Assignee: STMicroelectronics S.A.
    Inventor: Pietro Fichera
  • Protection of a power transistor
    Publication number: 20060250742
    Abstract: A method and a circuit for protecting a transistor that controls the supply of an at least partially inductive load, including lowering the demagnetization voltage of the inductive load with respect to a demagnetization voltage set by a break-over component connected between a conduction terminal and the control terminal of the transistor.
    Type: Application
    Filed: October 27, 2005
    Publication date: November 9, 2006
    Applicant: STMicroelectronics S.A.
    Inventor: Pietro Fichera
  • Component of protection of an integrated MOS power transistor against voltage gradients
    Patent number: 6057577
    Abstract: The present invention relate to a device of protection against voltage gradients of a monolithic component including a vertical MOS power transistor and logic circuits. The protection circuit has an N-type substrate corresponding to the drain of the MOS transistor, and logic components being realized in at least one P-type well formed in the upper surface of the substrate. Each of the N-type regions connected to the ground of the logic circuit, or to a node of low impedance with respect to the ground, is in series with a resistor.
    Type: Grant
    Filed: May 27, 1998
    Date of Patent: May 2, 2000
    Assignee: STMicroelectronics S.A.
    Inventors: Jean Barret, Antoine Pavlin, Pietro Fichera