Patents by Inventor PIN HU

PIN HU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11967546
    Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Yun Hou, Hsien-Pin Hu, Sao-Ling Chiu, Wen-Hsin Wei, Ping-Kang Huang, Chih-Ta Shen, Szu-Wei Lu, Ying-Ching Shih, Wen-Chih Chiou, Chi-Hsi Wu, Chen-Hua Yu
  • Publication number: 20240123479
    Abstract: A recycling apparatus for a solar cell module includes a platform for supporting and positioning the solar cell module, and at least one milling device disposed on the platform and having a milling member configured to contact a back plate of the solar cell module, and a casing defining a chip-receiving space and having an air inlet and a suction port communicating with the chip-receiving space. A drive device is connected to the at least one milling device for driving the at least one milling device to move around and mill the solar cell module through the milling member.
    Type: Application
    Filed: October 28, 2021
    Publication date: April 18, 2024
    Applicant: NATIONAL UNIVERSITY OF TAINAN
    Inventors: Yao-Hsien FU, Hsueh-Pin TAI, Chia-Tsung HUNG, Cheng-Chen LIU, Chun-Chih HU, How-Wei KE
  • Publication number: 20240105632
    Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 28, 2024
    Inventors: Hsien-Pin Hu, Chen-Hua Yu, Ming-Fa Chen, Jing-Cheng Lin, Jiun Ren Lai, Yung-Chi Lin
  • Publication number: 20240105627
    Abstract: Semiconductor devices and methods of manufacture are provided. In embodiments the semiconductor device includes a substrate, a first interposer bonded to the substrate, a second interposer bonded to the substrate, a bridge component electrically connecting the first interposer to the second interposer, two or more first dies bonded to the first interposer; and two or more second dies bonded to the second interposer.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 28, 2024
    Inventors: Shang-Yun Hou, Hsien-Pin Hu
  • Publication number: 20240088093
    Abstract: In an embodiment, a method includes: attaching a package component to a package substrate, the package component includes: a first die being disposed over an interposer; a second die being disposed over the interposer and laterally adjacent to the first die; and an encapsulant being disposed around the first die and the second die; attaching a thermal interface material to the first die and the second die; and attaching a lid structure to the package substrate, the lid structure includes: a lid cap being disposed over the thermal interface material; and a plurality of lid feet connecting the lid cap to the package substrate, in a plan view the plurality of lid feet forming a discontinuous loop around the package component.
    Type: Application
    Filed: January 4, 2023
    Publication date: March 14, 2024
    Inventors: Wensen Hung, Tsung-Yu Chen, Wen-Hsin Wei, Hsien-Pin Hu
  • Patent number: 11923310
    Abstract: A package structure and method for forming the same are provided. The package structure includes a first through via structure formed in a substrate and a semiconductor die formed below the first through via structure. The package structure further includes a conductive structure formed in a passivation layer over the substrate. The conductive structure includes a first via portion and a second via portion, the first via portion is directly over the first through via structure, and there is no conductive material directly below and in direct contact with the second via portion.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Kai Cheng, Tsung-Shu Lin, Tsung-Yu Chen, Hsien-Pin Hu, Wen-Hsin Wei
  • Patent number: 11916031
    Abstract: A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chia Hu, Ching-Pin Yuan, Sung-Feng Yeh, Sen-Bor Jan, Ming-Fa Chen
  • Publication number: 20240002573
    Abstract: The invention relates to medical aids, in particular compression products, such as compression stockings or bandages. Specifically, the invention provides a compression product comprising an elastic component or material that comprises polyurethane polymers and shows a delayed continuous relaxation behaviour. The invention furthermore provides polyurethane polymers containing N-diol having a delayed continuous relaxation behavior and corresponding quaternized polyurethane polymers, a process for producing the polyurethane polymers, a blend with elastane, as well as uses thereof.
    Type: Application
    Filed: July 15, 2023
    Publication date: January 4, 2024
    Inventors: CHRISTA HUGER, ANGELIKA SCHERM, SEEMA AGARWAL, ANDREAS GREINER, PIN HU
  • Patent number: 11854990
    Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Pin Hu, Chen-Hua Yu, Ming-Fa Chen, Jing-Cheng Lin, Jiun Ren Lai, Yung-Chi Lin
  • Patent number: 11854983
    Abstract: Semiconductor devices and methods of manufacture are provided. In embodiments the semiconductor device includes a substrate, a first interposer bonded to the substrate, a second interposer bonded to the substrate, a bridge component electrically connecting the first interposer to the second interposer, two or more first dies bonded to the first interposer; and two or more second dies bonded to the second interposer.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Yun Hou, Hsien-Pin Hu
  • Patent number: 11830745
    Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: November 28, 2023
    Assignee: TAIWANN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Wei Chiu, Cheng-Hsien Hsieh, Hsien-Pin Hu, Kuo-Ching Hsu, Shang-Yun Hou, Shin-Puu Jeng
  • Publication number: 20230369162
    Abstract: An apparatus for manufacturing packaged semiconductor devices includes a lower plate having package platforms and clamp guide pins to align an upper plate with the lower plate, and a boat tray having windows configured to receive package devices, and a plurality of upper plates configured to be aligned to respective windows and respective package platforms. Clamping force can be applied by fasteners configured to generate a downward force upon the upper plate. Package devices on the platforms are thus subjected to a clamping force. Load cells measure the clamping force so adjustments can be made.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 16, 2023
    Inventors: Wensen Hung, Tsung-Yu Chen, Tsung-Shu Lin, Chen-Hsiang Lao, Wen-Hsin Wei, Hsien-Pin Hu
  • Patent number: 11810833
    Abstract: A packaged semiconductor device and a method and apparatus for forming the same are disclosed. In an embodiment, a method includes bonding a device die to a first surface of a substrate; depositing an adhesive on the first surface of the substrate; depositing a thermal interface material on a surface of the device die opposite the substrate; placing a lid over the device die and the substrate, the lid contacting the adhesive and the thermal interface material; applying a clamping force to the lid and the substrate; and while applying the clamping force, curing the adhesive and the thermal interface material.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: November 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wensen Hung, Tsung-Yu Chen, Tsung-Shu Lin, Chen-Hsiang Lao, Wen-Hsin Wei, Hsien-Pin Hu
  • Patent number: 11777542
    Abstract: A method for tuning an envelope tracking (ET) system includes: determining a setting combination from a plurality of setting available to the ET system, wherein determining the setting combination from the plurality of setting available to the ET system includes: determining, by a processing module, a first setting in a plurality of first settings included in the plurality of settings, and configuring the ET system by the first setting; and after the ET system is configured by the first setting, determining, by the processing module, a second setting in a plurality of second settings included in the plurality of settings, and configuring the ET system by the second setting. In addition, the setting combination includes the first setting and the second setting.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: October 3, 2023
    Assignee: MEDIATEK INC.
    Inventors: Ting-Hsun Kuo, Tsung-Pin Hu, Wei-Che Tseng, Chih-Chia Wang
  • Patent number: 11746179
    Abstract: The invention relates to medical aids, in particular compression products, such as compression stockings or bandages. More specifically, the invention relates to compression products comprising fibre forming polyurethane polymers showing a delayed continuous relaxation behaviour. The invention furthermore relates to polyurethane polymers containing N-diol and corresponding quaternised polyurethane polymers, to a process of producing the polyurethane polymers, to blends with elastane, as well as to uses.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: September 5, 2023
    Assignee: MEDI GMBH & CO. KG
    Inventors: Christa Huger, Angelika Scherm, Seema Agarwal, Andreas Greiner, Pin Hu
  • Publication number: 20230260896
    Abstract: A device package including an interposer. The interposer comprising: a semiconductor substrate; first through vias extending through the semiconductor substrate; an interconnect structure comprising: a first metallization pattern in an inorganic insulating material; and a passivation film over the first metallization pattern; and a first redistribution structure over the passivation film. The first redistribution structure comprising a second metallization pattern in an organic insulating material. The device package further including an integrated circuit die over and attached to the interposer; and a first encapsulant around the integrated circuit die.
    Type: Application
    Filed: June 10, 2022
    Publication date: August 17, 2023
    Inventors: Hsien-Pin Hu, Shang-Yun Hou, Shih-Wen Huang
  • Patent number: 11728254
    Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shang-Yun Hou, Hsien-Pin Hu, Sao-Ling Chiu, Wen-Hsin Wei, Ping-Kang Huang, Chih-Ta Shen, Szu-Wei Lu, Ying-Ching Shih, Wen-Chih Chiou, Chi-Hsi Wu, Chen-Hua Yu
  • Patent number: 11682593
    Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: June 20, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzuan-Horng Liu, Chen-Hua Yu, Hsien-Pin Hu, Tzu-Yu Wang, Wei-Cheng Wu, Shang-Yun Hou, Shin-Puu Jeng
  • Publication number: 20230052147
    Abstract: Provided herein are methods and kits for detecting the presence of DNA and/or RNA mutations associated with cancer (e.g., lung cancer). The methods and kits employ microcarriers, each with a probe specific for a DNA or RNA mutation and an identifier unique to the probe sequence. Upon isolation and amplification of nucleic acids from a sample, hybridization of amplified DNA with a probe, specific for a DNA or RNA mutation, that is coupled to a microcarrier indicates the presence of the mutation in the sample. Since each microcarrier can be identified through detection of the identifier, multiplex screening assays are provided. Representative genes that can be screened for mutations include, e.g., KRAS, NRAS, PIK3CA, BRAF, EGFR, AKT1, MEK1, and HER2 for DNA mutations and/or ALK, ROS, RET, NTRK1, and cMET for RNA mutations.
    Type: Application
    Filed: January 7, 2021
    Publication date: February 16, 2023
    Applicant: PLEXBIO CO., LTD.
    Inventors: Dean TSAO, Chin-Shiou HUANG, Shian Pin HU, Fei-Yu CHANG, Yi Ling HSIEH
  • Patent number: 11569172
    Abstract: Semiconductor devices and methods of manufacture are provided. In embodiments the semiconductor device includes a substrate, a first interposer bonded to the substrate, a second interposer bonded to the substrate, a bridge component electrically connecting the first interposer to the second interposer, two or more first dies bonded to the first interposer; and two or more second dies bonded to the second interposer.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shang-Yun Hou, Hsien-Pin Hu