Patents by Inventor Pin-Shiang Chen
Pin-Shiang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11664218Abstract: A transistor based on topological insulators is provided. In an embodiment a topological insulator is used to form both the channel as well as the source/drain regions, wherein the channel has a first thickness such that the topological insulator material has properties of a semiconductor material and the source/drain regions have a second thickness such that the topological insulator has properties of a conductive material.Type: GrantFiled: June 7, 2021Date of Patent: May 30, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Sheng-Ting Fan, Pin-Shiang Chen, Chee Wee Liu, Chi-Wen Liu
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Patent number: 11374115Abstract: A method includes forming a first semiconductor layer over a substrate; forming a second semiconductor layer over the first semiconductor layer; forming a dummy gate structure over the second semiconductor layer; performing an etching process to form a recess in the first and second semiconductor layers; forming a epitaxy structure over in the recess, wherein the epitaxy structure is in contact with the first and second semiconductor layers; performing a solid phase diffusion process to form a doped region in the epitaxy structure, in which the doped region is in contact with the second semiconductor layer and is separated from the first semiconductor layer; and replacing the dummy gate structure with a metal gate structure.Type: GrantFiled: September 11, 2020Date of Patent: June 28, 2022Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Chung-En Tsai, Fang-Liang Lu, Pin-Shiang Chen, Chee-Wee Liu
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Publication number: 20210296112Abstract: A transistor based on topological insulators is provided. In an embodiment a topological insulator is used to form both the channel as well as the source/drain regions, wherein the channel has a first thickness such that the topological insulator material has properties of a semiconductor material and the source/drain regions have a second thickness such that the topological insulator has properties of a conductive material.Type: ApplicationFiled: June 7, 2021Publication date: September 23, 2021Inventors: Sheng-Ting Fan, Pin-Shiang Chen, Chee Wee Liu, Chi-Wen Liu
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Patent number: 11043376Abstract: A transistor based on topological insulators is provided. In an embodiment a topological insulator is used to form both the channel as well as the source/drain regions, wherein the channel has a first thickness such that the topological insulator material has properties of a semiconductor material and the source/drain regions have a second thickness such that the topological insulator has properties of a conductive material.Type: GrantFiled: April 14, 2020Date of Patent: June 22, 2021Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan UniversityInventors: Sheng-Ting Fan, Pin-Shiang Chen, Chee Wee Liu, Chi-Wen Liu
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Patent number: 11018239Abstract: A semiconductor device includes a channel, source/drain structures, and a gate stack. The source/drain structures are on opposite sides of the channel. The gate stack is over the channel, and the gate stack includes a gate dielectric layer, a doped ferroelectric layer, and a gate electrode. The gate dielectric layer is over the channel. The doped ferroelectric layer is over the gate dielectric layer. The gate electrode is over the doped ferroelectric layer. A dopant concentration of the doped ferroelectric layer varies in a direction from the gate electrode toward the channel.Type: GrantFiled: April 13, 2019Date of Patent: May 25, 2021Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL CHIAO TUNG UNIVERSITYInventors: Pin-Shiang Chen, Sheng-Ting Fan, Chee-Wee Liu
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Publication number: 20200411671Abstract: A method includes forming a first semiconductor layer over a substrate; forming a second semiconductor layer over the first semiconductor layer; forming a dummy gate structure over the second semiconductor layer; performing an etching process to form a recess in the first and second semiconductor layers; forming a epitaxy structure over in the recess, wherein the epitaxy structure is in contact with the first and second semiconductor layers; performing a solid phase diffusion process to form a doped region in the epitaxy structure, in which the doped region is in contact with the second semiconductor layer and is separated from the first semiconductor layer; and replacing the dummy gate structure with a metal gate structure.Type: ApplicationFiled: September 11, 2020Publication date: December 31, 2020Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Chung-En TSAI, Fang-Liang LU, Pin-Shiang CHEN, Chee-Wee LIU
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Patent number: 10879404Abstract: A device includes a semiconductor substrate, a buried oxide over the substrate, a first transition metal dichalcogenide layer over the buried oxide, an insulator over the first transition metal dichalcogenide layer, and a second transition metal dichalcogenide layer over the insulator. A gate dielectric is over the second transition metal dichalcogenide layer, and a gate is over the gate dielectric.Type: GrantFiled: April 22, 2019Date of Patent: December 29, 2020Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan UniversityInventors: Pin-Shiang Chen, Hung-Chih Chang, Chee-Wee Liu, Samuel C. Pan
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Publication number: 20200328287Abstract: A semiconductor device includes a channel, source/drain structures, and a gate stack. The source/drain structures are on opposite sides of the channel. The gate stack is over the channel, and the gate stack includes a gate dielectric layer, a doped ferroelectric layer, and a gate electrode. The gate dielectric layer is over the channel. The doped ferroelectric layer is over the gate dielectric layer. The gate electrode is over the doped ferroelectric layer. A dopant concentration of the doped ferroelectric layer varies in a direction from the gate electrode toward the channel.Type: ApplicationFiled: April 13, 2019Publication date: October 15, 2020Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL CHIAO TUNG UNIVERSITYInventors: Pin-Shiang CHEN, Sheng-Ting FAN, Chee-Wee LIU
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Patent number: 10777663Abstract: A method includes forming a fin structure over a substrate; forming a source/drain structure adjoining the fin structure, in which the source/drain structure includes tin; and exposing the source/drain structure to a boron-containing gas to diffuse boron into the source/drain structure to form a doped region in the source/drain structure.Type: GrantFiled: October 2, 2018Date of Patent: September 15, 2020Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Chung-En Tsai, Fang-Liang Lu, Pin-Shiang Chen, Chee-Wee Liu
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Publication number: 20200243327Abstract: A transistor based on topological insulators is provided. In an embodiment a topological insulator is used to form both the channel as well as the source/drain regions, wherein the channel has a first thickness such that the topological insulator material has properties of a semiconductor material and the source/drain regions have a second thickness such that the topological insulator has properties of a conductive material.Type: ApplicationFiled: April 14, 2020Publication date: July 30, 2020Inventors: Sheng-Ting Fan, Pin-Shiang Chen, Chee Wee Liu, Chi-Wen Liu
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Patent number: 10636651Abstract: A transistor based on topological insulators is provided. In an embodiment a topological insulator is used to form both the channel as well as the source/drain regions, wherein the channel has a first thickness such that the topological insulator material has properties of a semiconductor material and the source/drain regions have a second thickness such that the topological insulator has properties of a conductive material.Type: GrantFiled: July 31, 2018Date of Patent: April 28, 2020Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan UniversityInventors: Sheng-Ting Fan, Pin-Shiang Chen, Chee Wee Liu, Chi-Wen Liu
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Publication number: 20190252554Abstract: A device includes a semiconductor substrate, a buried oxide over the substrate, a first transition metal dichalcogenide layer over the buried oxide, an insulator over the first transition metal dichalcogenide layer, and a second transition metal dichalcogenide layer over the insulator. A gate dielectric is over the second transition metal dichalcogenide layer, and a gate is over the gate dielectric.Type: ApplicationFiled: April 22, 2019Publication date: August 15, 2019Inventors: Pin-Shiang Chen, Hung-Chih Chang, Chee Wee Liu, Samuel C. Pan
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Publication number: 20190165141Abstract: A method includes forming a fin structure over a substrate; forming a source/drain structure adjoining the fin structure, in which the source/drain structure includes tin; and exposing the source/drain structure to a boron-containing gas to diffuse boron into the source/drain structure to form a doped region in the source/drain structure.Type: ApplicationFiled: October 2, 2018Publication date: May 30, 2019Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Chung-En TSAI, Fang-Liang LU, Pin-Shiang CHEN, Chee-Wee LIU
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Patent number: 10290708Abstract: Semiconductor devices and methods of forming the same are provided. A first gate electrode layer is formed over a substrate. A first gate dielectric layer is formed over the first gate electrode layer. A first channel layer is formed over the first gate dielectric layer. An isolation layer is formed over the first channel layer. A second channel layer is formed over the isolation layer. A second gate dielectric layer is formed over the second channel layer. The second gate dielectric layer, the second channel layer, the isolation layer and the first channel layer are patterned to form a first opening, the first opening extending through the first gate dielectric layer, the second channel layer and the isolation layer, and into the first channel layer. A first source/drain region is formed in the first opening.Type: GrantFiled: October 21, 2016Date of Patent: May 14, 2019Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan UniversityInventors: Pin-Shiang Chen, Samuel C. Pan, Chee-Wee Liu, Sheng-Ting Fan
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Patent number: 10269981Abstract: A device includes a semiconductor substrate, a buried oxide over the substrate, a first transition metal dichalcogenide layer over the buried oxide, an insulator over the first transition metal dichalcogenide layer, and a second transition metal dichalcogenide layer over the insulator. A gate dielectric is over the second transition metal dichalcogenide layer, and a gate is over the gate dielectric.Type: GrantFiled: November 17, 2014Date of Patent: April 23, 2019Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan UniversityInventors: Pin-Shiang Chen, Hung-Chih Chang, Chee-Wee Liu, Samuel C. Pan
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Publication number: 20180337032Abstract: A transistor based on topological insulators is provided. In an embodiment a topological insulator is used to form both the channel as well as the source/drain regions, wherein the channel has a first thickness such that the topological insulator material has properties of a semiconductor material and the source/drain regions have a second thickness such that the topological insulator has properties of a conductive material.Type: ApplicationFiled: July 31, 2018Publication date: November 22, 2018Inventors: Sheng-Ting Fan, Pin-Shiang Chen, Chee Wee Liu, Chi-Wen Liu
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Patent number: 10109477Abstract: A transistor based on topological insulators is provided. In an embodiment a topological insulator is used to form both the channel as well as the source/drain regions, wherein the channel has a first thickness such that the topological insulator material has properties of a semiconductor material and the source/drain regions have a second thickness such that the topological insulator has properties of a conductive material.Type: GrantFiled: May 10, 2016Date of Patent: October 23, 2018Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan UniversityInventors: Sheng-Ting Fan, Pin-Shiang Chen, Chee Wee Liu, Chi-Wen Liu
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Publication number: 20170194470Abstract: A transistor based on topological insulators is provided. In an embodiment a topological insulator is used to form both the channel as well as the source/drain regions, wherein the channel has a first thickness such that the topological insulator material has properties of a semiconductor material and the source/drain regions have a second thickness such that the topological insulator has properties of a conductive material.Type: ApplicationFiled: May 10, 2016Publication date: July 6, 2017Inventors: Sheng-Ting Fan, Pin-Shiang Chen, Chee Wee Liu, Chi-Wen Liu
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Patent number: 9679961Abstract: A device includes a source region, a drain region, and a wurtzite semiconductor between the source region and the drain region. A source-drain direction is parallel to a [01-10] direction or a [?2110] direction of the wurtzite semiconductor. The device further includes a gate dielectric over the wurtzite semiconductor, and a gate electrode over the gate dielectric.Type: GrantFiled: July 27, 2016Date of Patent: June 13, 2017Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan UniversityInventors: Hung-Chih Chang, Pin-Shiang Chen, Chee-Wee Liu, Samuel C. Pan
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Patent number: 9660056Abstract: A semiconductor device and a method of manufacture are provided. A substrate has a dielectric layer formed thereon. A three-dimensional feature, such as a trench or a fin, is formed in the dielectric layer. A two-dimensional layer, such as a layer (or multilayer) of graphene, transition metal dichalcogenides (TMDs), or boron nitride (BN), is formed over sidewalls of the feature. The two-dimensional layer may also extend along horizontal surfaces, such as along a bottom of the trench or along horizontal surfaces of the dielectric layer extending away from the three-dimensional feature. A gate dielectric layer is formed over the two-dimensional layer and a gate electrode is formed over the gate dielectric layer. Source/drain contacts are electrically coupled to the two-dimensional layer on opposing sides of the gate electrode.Type: GrantFiled: January 7, 2016Date of Patent: May 23, 2017Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan UniversityInventors: Hung-Chih Chang, Pin-Shiang Chen, Chee-Wee Liu