Abstract: A semiconductor apparatus and a method for collecting residues of curable material are provided. The semiconductor apparatus includes a chamber containing a wafer cassette, and a collecting module disposed in the chamber for collecting residues of curable material in the chamber. The collecting module includes a flow-directing structure disposed below a ceiling of the chamber, a baffle structure disposed below the flow-directing structure, and a tray disposed on the wafer cassette. The flow-directing structure includes a first hollow region, the baffle structure includes a second hollow region, and the tray is moved together with the wafer cassette to pass through the second hollow region of the baffle structure and is positioned to cover the first hollow region of the flow-directing structure.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip processing tool. The integrated chip processing tool includes a first transfer module and a second transfer module. The first transfer module has a first robotic arm disposed within a housing. The first transfer module is configured to receive a single and unitary first die tray configured to hold a plurality of integrated chip (IC) die and to concurrently transfer all of the plurality of IC die held by the single and unitary first die tray to a single and unitary die boat. The second transfer module has an additional robotic arm disposed within the housing and configured to concurrently transfer all of the plurality of IC die from the single and unitary die boat to a single and unitary second die tray.

Abstract: Present disclosure provides a method for forming a semiconductor packaged wafer, including providing a semiconductor package having a die on a first side of a wafer, partially molding the die by disposing molding material on the first side of the wafer, a peripheral of the first side is free of molding material at a completion of the partially molding, and bonding the semiconductor package with a carrier from the first side of the wafer. Present disclosure also provides a semiconductor packaged wafer, including a die on a first side of a wafer, a molding encapsulating the die and partially positioning on the first side of the wafer by retracting from a peripheral of the first side of the wafer, and a sealing structure on the peripheral of the first side of the wafer.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip processing tool. The integrated chip processing tool includes a first transfer module and a second transfer module. The first transfer module has a first robotic arm disposed within a housing. The first transfer module is configured to receive a single and unitary first die tray configured to hold a plurality of integrated chip (IC) die and to concurrently transfer all of the plurality of IC die held by the single and unitary first die tray to a single and unitary die boat. The second transfer module has an additional robotic arm disposed within the housing and configured to concurrently transfer all of the plurality of IC die from the single and unitary die boat to a single and unitary second die tray.

Abstract: The present disclosure relates to an integrated chip (IC) processing tool having a die exchanger configured to automatically transfer a plurality of IC die between a die tray and a die boat, and an associated method. The integrated chip processing tool has a die exchanger configured to receive a die tray comprising a plurality of IC die. The die exchanger is configured to automatically transfer the plurality of IC die between the die tray and a die boat. An IC die processing tool is configured to receive the die boat from the die exchanger and to perform a processing step on the plurality of IC die within the die boat. By operating the die exchanger to automatically transfer IC die between the die tray and the die boat, the transfer time can be reduced and contamination and/or damage risks related to a manual transfer of IC die can be mitigated.

Abstract: Present disclosure provides a method for forming a semiconductor packaged wafer, including providing a semiconductor package having a die on a first side of a wafer, partially molding the die by disposing molding material on the first side of the wafer, a peripheral of the first side is free of molding material at a completion of the partially molding, and bonding the semiconductor package with a carrier from the first side of the wafer. Present disclosure also provides a semiconductor packaged wafer, including a die on a first side of a wafer, a molding encapsulating the die and partially positioning on the first side of the wafer by retracting from a peripheral of the first side of the wafer, and a sealing structure on the peripheral of the first side of the wafer.

Abstract: The present disclosure relates to an integrated chip (IC) processing tool having a die exchanger configured to automatically transfer a plurality of IC die between a die tray and a die boat, and an associated method. The integrated chip processing tool has a die exchanger configured to receive a die tray comprising a plurality of IC die. The die exchanger is configured to automatically transfer the plurality of IC die between the die tray and a die boat. An IC die processing tool is configured to receive the die boat from the die exchanger and to perform a processing step on the plurality of IC die within the die boat. By operating the die exchanger to automatically transfer IC die between the die tray and the die boat, the transfer time can be reduced and contamination and/or damage risks related to a manual transfer of IC die can be mitigated.

Abstract: An improved method of patterning resist protective dielectric layer and preferably protective silicon dioxide layer is described. The method consists of two sequential etching steps, the first one being a timed plasma etching process and the second one being a timed wet etching process. Plasma etching is used to remove approximately 70%–90% of the RPO film thickness and wet etching is used to remove the remaining 10%–30% of the film thickness. The two-step etching process achieves superior dimensional control, a non-undercut profile under the resist mask and prevents resist mask peeling from failure of adhesion at the mask/RPO film interface. The improved method has wide applications wherever and whenever RPO film is used in the process flow for fabricating semiconductor devices.

Abstract: A method of fabricating final spacers having a target width comprises the following steps. Initial spacers, each having an initial width that is less than the target width, are formed over the opposing side walls of a gate electrode portion. The difference between the initial spacer width and the target width is determined. A second spacer layer having a thickness equal to the determined difference between the initial width of the initial spacers and the target width is formed upon the initial spacers and the structure. The second spacer layer is etched to leave second spacer layer portions extending from the initial spacers to form the final spacers.

Abstract: A method for fabricating aluminum bonding pads is described. A passivation layer is provided overlying semiconductor device structures in and on a substrate. A bonding pad layer is deposited overlying the passivation layer and within openings in the passivation layer to underlying semiconductor device structures. A masking layer is formed overlying the bonding pad layer wherein the masking layer has a pattern of bonding pads and a dummy pattern wherein a density of the bonding pad pattern and the dummy pattern together is 20% or more. The bonding pad layer is etched away where it is not covered by the masking layer to form bonding pads contacting the semiconductor device structures and dummy pads not contacting the semiconductor device structures wherein the pattern density of 20% or more reduces plasma damage by reducing an etching rate of the bonding pad layer compared to a pattern density of less than 20%.

Abstract: A method of fabricating final spacers having a target width comprises the following steps. Initial spacers, each having an initial width that is less than the target width, are formed over the opposing side walls of a gate electrode portion. The difference between the initial spacer width and the target width is determined. A second spacer layer having a thickness equal to the determined difference between the initial width of the initial spacers and the target width is formed upon the initial spacers and the structure. The second spacer layer is etched to leave second spacer layer portions extending from the initial spacers to form the final spacers.

Abstract: A deep ultraviolet (UV) light-resistant photoresist plug for via holes, as may be used in damascene, dual-damascene, and other types of semiconductor fabrication processing, is disclosed. A via hole of a semiconductor wafer is partially plugged with non-photosensitive photoresist, such as negative photoresist. The via hole and the wafer are then coated with a deep UV light-sensitive photoresist. The deep UV light-sensitive photoresist is exposed to deep UV light, such as 193 nanometer (nm) wavelength light, where the non-photosensitive photoresist is unresponsive to the deep UV light. The wafer is then developed to selectively remove the deep UV light-sensitive photoresist, where the non-photosensitive photoresist substantially remains.

Abstract: An improved method of patterning resist protective dielectric layer and preferably protective silicon dioxide layer is described. The method consists of two sequential etching steps, the first one being a timed plasma etching process and the second one being a timed wet etching process. Plasma etching is used to remove approximately 70%-90% of the RPO film thickness and wet etching is used to remove the remaining 10%-30% of the film thickness. The two-step etching process achieves superior dimensional control, a non-undercut profile under the resist mask and prevents resist mask peeling from failure of adhesion at the mask/RPO film interface. The improved method has wide applications wherever and whenever RPO film is used in the process flow for fabricating semiconductor devices.

Abstract: A deep ultraviolet (UV) light-resistant photoresist plug for via holes, as may be used in damascene, dual-damascene, and other types of semiconductor fabrication processing, is disclosed. A via hole of a semiconductor wafer is partially plugged with non-photosensitive photoresist, such as negative photoresist. The via hole and the wafer are then coated with a deep UV light-sensitive photoresist. The deep UV light-sensitive photoresist is exposed to deep UV light, such as 193 nanometer (nm) wavelength light, where the non-photosensitive photoresist is unresponsive to the deep UV light. The wafer is then developed to selectively remove the deep UV light-sensitive photoresist, where the non-photosensitive photoresist substantially remains.

Abstract: A method for plasma etching a semiconductor feature to improve an etching profile including providing a semiconductor wafer comprising a first feature opening anisotropically etched though a thickness portion of at least one dielectric insulating layer; anisotropically etching a second feature opening overlying and at least partially encompassing the first feature opening according to a reactive ion etch (RIE) process to leave an unetched portion surrounding a first feature opening portion at about a bottom portion level of the second feature opening; and, plasma treating the first and second openings with a plasma formed of a mixture of oxygen and nitrogen plasma source gases including an applying an independently variable RF bias power source to the semiconductor wafer to remove the unetched portion.

Abstract: An undesirable side effect of some processes that are used for forming dual gate devices is the formation of defects at the interface between the two oxide layers of different thickness. This problem has been solved by preceding the HF wet dip (that is used to thin out a selected area of oxide) with exposure of the photoresist to a low power plasma that includes some oxygen. This treatment removes unsaturated chemical bonds from the resist surface and prevents the formation of SiC based defects. Such defects could cause polysilicon lines to short or open, depending on their size.

Abstract: Within a method for forming a plasma etched layer, there is first provided a substrate. There is then formed over the substrate a microelectronic layer. There is then etched within a plasma reactor chamber, and while employing a plasma etch method, the microelectronic layer to form a plasma etched microelectronic layer. Finally, there is then purged the plasma reactor chamber with an inert purge gas, without subsequently evacuating the plasma reactor chamber, prior to removing the substrate having formed thereover the plasma etched microelectronic layer from the plasma reactor chamber. In an alternative there is purged a load lock chamber integral to the plasma reactor chamber with an inert purge gas, without subsequently evacuating the load lock chamber, prior to removing the substrate having formed thereover the plasma etched microelectronic layer from the load lock chamber.