Abstract: A scribe line structure between die regions is disclosed. The scribe line structure includes a dielectric layer disposed on a substrate; and a plurality of metal structures arranged up-and-down in the dielectric layer on the substrate, the plurality of metal structures comprising metal layers and metal vias, wherein the metal vias are disposed on the dicing path and regions outside the dicing path and the metal vias on the dicing path have a lower metal density than the metal vias not on the dicing path.

Abstract: A scribe line structure between die regions is disclosed. The scribe line structure includes a dielectric layer disposed on a substrate; and a plurality of metal structures arranged up-and-down in the dielectric layer on the substrate, the plurality of metal structures comprising metal layers and metal vias, wherein the metal vias are disposed on the dicing path and regions outside the dicing path and the metal vias on the dicing path have a lower metal density than the metal vias not on the dicing path.

Abstract: The scribe line structure for wafer dicing according to the present invention includes a plurality of metal structures arranged up-and-down on a substrate in a dielectric layer, and an upper one of the metal structures has a lower metal density than a lower one of the metal structures. In another aspect, the scribe line structure for wafer dicing includes a plurality of metal structures arranged up-and-down on a substrate in a dielectric layer, and each of the metal structures has a lower metal density on a dicing path for the wafer dicing than not on the dicing path. The scribe line structure can effectively avoid interlayer delamination or peeling issue caused by a dicing process, especially on a low-k/Cu wafer.

Abstract: A test pad structure on a wafer includes at least a scribe line positioned on a wafer, a pad region defined in the scribe line, and a metal pad positioned in the pad region. An area of the metal pad and an area of the pad region include a ratio, and the ratio is lower than equal to 50%.

Abstract: A bond pad structure located over an active circuit structure is disclosed. The bond pad structure includes a bond pad, a passivation layer and a topmost metal layer in the active circuit structure. The passivation layer covers the bond pad and has an opening, and the opening exposes a part of the bond pad. The part of the topmost metal layer located under the opening serves as a supporting layer. The supporting layer has at least a slot, and the topmost metal layer is electrically connected to the bond pad through a plurality of via plugs.

Abstract: The scribe line structure for wafer dicing according to the present invention includes a plurality of metal structures arranged up-and-down on a substrate in a dielectric layer, and an upper one of the metal structures has a lower metal density than a lower one of the metal structures. In another aspect, the scribe line structure for wafer dicing includes a plurality of metal structures arranged up-and-down on a substrate in a dielectric layer, and each of the metal structures has a lower metal density on a dicing path for the wafer dicing than not on the dicing path. The scribe line structure can effectively avoid interlayer delamination or peeling issue caused by a dicing process, especially on a low-k/Cu wafer.

Abstract: A scribe line structure is disclosed. The scribe line structure includes a semiconductor substrate having a die region, a die seal ring region, disposed outside the die region, a scribe line region disposed outside the die seal ring region and a dicing path formed on the scribe line region. Preferably, the center line of the dicing path is shifted away from the center line of the scribe line region along a first direction.

Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a dielectric layer, a conductive structure, a low-k dielectric layer and a plug. The conductive structure is disposed in the dielectric layer, having a recess portion. The low-k dielectric layer is disposed on the dielectric layer. The plug is disposed in the low-k dielectric layer and has a protruding bonding portion on the bottom of the plug. The bonding portion is extended into the dielectric layer and connected to the recess portion of the conductive structure.

Abstract: The scribe line structure for wafer dicing according to the present invention includes a plurality of metal structures arranged up-and-down on a substrate in a dielectric layer, and an upper one of the metal structures has a lower metal density than a lower one of the metal structures. In another aspect, the scribe line structure for wafer dicing includes a plurality of metal structures arranged up-and-down on a substrate in a dielectric layer, and each of the metal structures has a lower metal density on a dicing path for the wafer dicing than not on the dicing path. The scribe line structure can effectively avoid interlayer delamination or peeling issue caused by a dicing process, especially on a low-k/Cu wafer.

Abstract: A scribe line structure is disclosed. The scribe line structure includes a semiconductor substrate having a die region, a die seal ring region, disposed outside the die region, a scribe line region disposed outside the die seal ring region and a dicing path formed on the scribe line region. Preferably, the center line of the dicing path is shifted away from the center line of the scribe line region along a first direction.

Abstract: A die seal ring disposed in a die and surrounding an integrated circuit region of the die is described. The die seal ring has at least two different local widths.

Abstract: A semiconductor wafer comprises a plurality of die areas, at least a first scribe line area and at least a second scribe line area surrounding each die area, at least a first metal structure positioned in the first scribe line area, and at least a second metal structure positioned in the second scribe line area. The first metal structure comprises at least a first slot split parallel to the first scribe line area, or comprises a plurality of openings arranged in an array. The second metal structure comprises at least a second slot split parallel to the second scribe line area, or comprises a plurality of openings arranged in an array.

Abstract: A semiconductor wafer comprises a plurality of die areas, at least a first scribe line area and at least a second scribe line area surrounding each die area, at least a first metal structure positioned in the first scribe line area, and at least a second metal structure positioned in the second scribe line area. The first metal structure comprises at least a first slot split parallel to the first scribe line area, or comprises a plurality of openings arranged in an array. The second metal structure comprises at least a second slot split parallel to the second scribe line area, or comprises a plurality of openings arranged in an array.

Abstract: A bond pad structure located over an active circuit structure is disclosed. The bond pad structure includes a bond pad, a passivation layer and a topmost metal layer in the active circuit structure. The passivation layer covers the bond pad and has an opening, and the opening exposes a part of the bond pad. The part of the topmost metal layer located under the opening serves as a supporting layer. The supporting layer has at least a slot, and the topmost metal layer is electrically connected to the bond pad through a plurality of via plugs.

Abstract: A method of reworking a chip includes providing a first chip and a second chip. The first and second chips have at least one first module and at least one second module, respectively. The first and second modules electrically connect with each other. The first module of the first chip has a defect. The second module of the second chip has a defect. The first module having a defect of the first chip is opened with the second module of the first chip, and the second module having a defect of the second chip is opened with the first module of the second chip. The first and second chips are stacked, and the second module of the first chip is electrically connects with the first module of the second chip.

Abstract: The scribe line structure for wafer dicing according to the present invention includes a plurality of metal structures arranged up-and-down on a substrate in a dielectric layer, and an upper one of the metal structures has a lower metal density than a lower one of the metal structures. In another aspect, the scribe line structure for wafer dicing includes a plurality of metal structures arranged up-and-down on a substrate in a dielectric layer, and each of the metal structures has a lower metal density on a dicing path for the wafer dicing than not on the dicing path. The scribe line structure can effectively avoid interlayer delamination or peeling issue caused by a dicing process, especially on a low-k/Cu wafer.

Abstract: A group probing over active area (POAA) pads arrangement includes a chip having a set of bonding pads, at least a first set of probing pads and a second set of probing pads. Each of the first set of probing pads and the second set of probing pads are electrically connected to one of the corresponding bonding pads, respectively. And each of the first set of probing pads and the second set of probing pads are interlaced in a diagonal line pattern. According to a concept of grouping and interlacing the probing pads, each bonding pad obtains at least two probing pads. Therefore times of test probing performed on each probing pad are reduced and repeated probe's pressures toward inter metal dielectric (IMD) layers underneath the probing pads are consequently reduced.

Abstract: A chip package structure including a substrate, a first chip and a second chip is provided. The first contacts and the second contacts of the substrate are respectively arranged to reside on a first side region and a second side region of the substrate. The first chip disposed on the substrate and has a plurality of first bonding pads arranged to reside on a first wire-bonding region of the first chip adjacent to the first contacts and are electrically connected to the first contacts via a plurality of first wires. The second chip is disposed on the first chip away from the symmetrical center of the first chip. The second chip has a plurality of second bonding pads arranged to reside on a second wire-bonding region of the second chip adjacent to the second contacts and are electrically connected to the second contacts via a plurality of second wires.

Abstract: A test IC structure is described, which is disposed in a scribe line region of a wafer and includes first and second test keys, first and second conductive plugs, first and second test pads, and a passivation layer over the scribe line region. The first/second test key includes a first/second active device and a first/second interconnect structure electrically connected thereto, wherein the second test key is arranged substantially parallel with the first one. The first/second plug is disposed over the first/second interconnect structure and contacts with the upmost metal layer thereof. The first/second test pad is disposed over the first and the second test keys and contacts with the first/second conductive plug. The passivation layer has therein a first opening exposing a portion of the first test pad and a second opening exposing a portion of the second test pad.

Abstract: A semiconductor chip is provided. The semiconductor chip includes a chip and chip bump pads thereon. The chip bump pads include at least two chip bump pads that are physically connected.