Patents by Inventor Ping-Chen CHANG
Ping-Chen CHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978570Abstract: An antioxidant conductive thermal paste and a method of manufacturing the same are provided. The antioxidant conductive thermal paste includes a reactive monomer, a thermosetting resin, a polymerization inhibitor, an electrically conductive filler, and a thixotropic agent. The method consists of the steps of mixing a reactive monomer, a thermosetting resin, and a polymerization inhibitor evenly to get a first polymer mixture, and adding an electrically conductive filler and a thixotropic agent into the first polymer mixture in turn and blending the mixture evenly to obtain an antioxidant conductive thermal paste with good adherence, high electrical conductivity, high thermal conductivity, improved thermal-mechanical fatigue resistance or mechanical fatigue resistance.Type: GrantFiled: August 21, 2023Date of Patent: May 7, 2024Assignee: Geckos Technology Corp.Inventors: Wei-Chen Chang, Chen-Yen Fan, Ping-Hung Chen, Tsung-Huan Sheng
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Patent number: 11961629Abstract: An antioxidant conductive thermal paste and a method of manufacturing the same are provided. The antioxidant conductive thermal paste includes a reactive monomer, a thermosetting resin, a polymerization inhibitor, an electrically conductive filler, and a thixotropic agent. The method consists of the steps of mixing a reactive monomer, a thermosetting resin, and a polymerization inhibitor evenly to get a first polymer mixture, and adding an electrically conductive filler and a thixotropic agent into the first polymer mixture in turn and blending the mixture evenly to obtain an antioxidant conductive thermal paste with good adherence, high electrical conductivity, high thermal conductivity, improved thermal-mechanical fatigue resistance or mechanical fatigue resistance.Type: GrantFiled: December 8, 2022Date of Patent: April 16, 2024Assignee: Geckos Technology Corp.Inventors: Wei-Chen Chang, Chen-Yen Fan, Ping-Hung Chen, Tsung-Huan Sheng
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Patent number: 11257807Abstract: A semiconductor device of electrostatic discharge (ESD) protection is provided, including a deep N-type region, disposed in a substrate; a deep P-type region, disposed in the substrate; a first P-type well, disposed in the deep N-type region; a first N-type well, abutting to the first P-type well, disposed in the deep N-type region. Further, a second P-type well abutting to the first N-type well is disposed in the deep P-type region. A second N-type well abutting to the second P-type well is disposed in the deep P-type region. A side N-type well is disposed in the deep N-type region at an outer side of the first P-type well. A side P-type well is disposed in the deep P-type region at an outer side of the second N-type well.Type: GrantFiled: December 3, 2020Date of Patent: February 22, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ting-Yao Lin, Chun Chiang, Ping-Chen Chang, Tien-Hao Tang
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Patent number: 10978442Abstract: An electrostatic discharge (ESD) protection device and a method thereof are presented. A well is disposed in a substrate. A gate is disposed on the well. A source region and a drain region are located in the well and at two opposite sides of the gate respectively. A first doped region is located in the drain region, wherein the first doped region is electrically connected to the drain region. A second doped region is located in the source region, wherein the second doped region is electrically connected to the source region. A third doped region is located in the well and at a side of the drain region opposite to the gate. A fourth doped region is located in the well and at a side of the source region opposite to the gate, wherein the fourth doped region is electrically connected to the third doped region.Type: GrantFiled: June 19, 2019Date of Patent: April 13, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ying-Wei Tseng, Chun Chiang, Ping-Chen Chang, Tien-Hao Tang
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Publication number: 20210091069Abstract: A semiconductor device of electrostatic discharge (ESD) protection is provided, including a deep N-type region, disposed in a substrate; a deep P-type region, disposed in the substrate; a first P-type well, disposed in the deep N-type region; a first N-type well, abutting to the first P-type well, disposed in the deep N-type region. Further, a second P-type well abutting to the first N-type well is disposed in the deep P-type region. A second N-type well abutting to the second P-type well is disposed in the deep P-type region. A side N-type well is disposed in the deep N-type region at an outer side of the first P-type well. A side P-type well is disposed in the deep P-type region at an outer side of the second N-type well.Type: ApplicationFiled: December 3, 2020Publication date: March 25, 2021Applicant: United Microelectronics Corp.Inventors: Ting-Yao Lin, Chun Chiang, Ping-Chen Chang, Tien-Hao Tang
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Patent number: 10903205Abstract: A semiconductor device of ESD protection includes a first P-type well in a substrate to receive a protected terminal and a first N-type well abutting the first P-type well in the substrate. A second P-type well abutting the first N-type well is in the substrate. A second N-type well abutting the second P-type well is in the substrate. A detective circuit device is formed on a surface of the substrate, having an input terminal to receive the protected terminal and an output terminal to provide a trigger voltage to the first N-type well. A first route structure is in the substrate, on a sidewall and a bottom of the first P-type well to connect to a bottom of the first N-type well. A second route structure is in the substrate, on sidewall and bottom of the second N-type well, to connect to a bottom of the second P-type well.Type: GrantFiled: April 25, 2019Date of Patent: January 26, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ting-Yao Lin, Chun Chiang, Ping-Chen Chang, Tien-Hao Tang
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Patent number: 10897131Abstract: An electrostatic discharge (ESD) protection circuit has a first power node, a second power node, an ESD detect circuit, an ESD device and a voltage controlled switch. The ESD detect circuit is coupled between the first power node and the second power node for detecting an ESD current to output a control signal at a output terminal of the ESD detect circuit. The ESD device is coupled between the first power node and the second power node for leaking the ESD current. The voltage controlled switch is used to couple a body of the ESD device to the second power node according to at least a voltage level of the control signal.Type: GrantFiled: January 24, 2018Date of Patent: January 19, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Cheng Liao, Ting-Yao Lin, Ping-Chen Chang, Tien-Hao Tang
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Publication number: 20200381415Abstract: An electrostatic discharge (ESD) protection device and a method thereof are presented. A well is disposed in a substrate. A gate is disposed on the well. A source region and a drain region are located in the well and at two opposite sides of the gate respectively. A first doped region is located in the drain region, wherein the first doped region is electrically connected to the drain region. A second doped region is located in the source region, wherein the second doped region is electrically connected to the source region. A third doped region is located in the well and at a side of the drain region opposite to the gate. A fourth doped region is located in the well and at a side of the source region opposite to the gate, wherein the fourth doped region is electrically connected to the third doped region.Type: ApplicationFiled: June 19, 2019Publication date: December 3, 2020Inventors: Ying-Wei Tseng, Chun Chiang, Ping-Chen Chang, Tien-Hao Tang
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Publication number: 20200343238Abstract: A semiconductor device of ESD protection includes a first P-type well in a substrate to receive a protected terminal and a first N-type well abutting the first P-type well in the substrate. A second P-type well abutting the first N-type well is in the substrate. A second N-type well abutting the second P-type well is in the substrate. A detective circuit device is formed on a surface of the substrate, having an input terminal to receive the protected terminal and an output terminal to provide a trigger voltage to the first N-type well. A first route structure is in the substrate, on a sidewall and a bottom of the first P-type well to connect to a bottom of the first N-type well. A second route structure is in the substrate, on sidewall and bottom of the second N-type well, to connect to a bottom of the second P-type well.Type: ApplicationFiled: April 25, 2019Publication date: October 29, 2020Applicant: United Microelectronics Corp.Inventors: Ting-Yao Lin, Chun Chiang, Ping-Chen Chang, Tien-Hao Tang
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Patent number: 10629585Abstract: An electrostatic discharge (ESD) protection device includes a substrate, a first gate group and a second gate group on the substrate, a drain region and a fourth doped region respectively at two sides of the first gate group, a source region and the fourth doped region respectively at two sides of the second gate group, a first doped region in the substrate and surrounded by the drain region, and a second doped region in the substrate and surrounded by the fourth doped region. The drain region and the source region have a first conductivity type. The first doped region and the second doped region have a second conductivity type complementary to the first conductivity type. The drain region is electrically connected to an input/output pad. The source region is electrically connected to a ground pad. The first doped region and the second doped region are electrically connected to each other.Type: GrantFiled: May 18, 2018Date of Patent: April 21, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Yu Huang, Kuan-Cheng Su, Tien-Hao Tang, Ping-Chen Chang
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Patent number: 10522530Abstract: An electrostatic discharge (ESD) shielding semiconductor device and an ESD testing method thereof, the ESD shielding semiconductor device includes an integrated circuit, a seal ring and a conductive layer. The integrated circuit is disposed on a die, and the integrated circuit has a first region and a second region. The seal ring is disposed on the die to surround the integrated circuit. The conductive layer at least covers the first region, and which is electrically connected to the seal ring.Type: GrantFiled: March 21, 2018Date of Patent: December 31, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun Chiang, Ying-Wei Tseng, Ping-Chen Chang, Tien-Hao Tang
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Publication number: 20190273077Abstract: An electrostatic discharge (ESD) shielding semiconductor device and an ESD testing method thereof, the ESD shielding semiconductor device includes an integrated circuit, a seal ring and a conductive layer. The integrated circuit is disposed on a die, and the integrated circuit has a first region and a second region. The seal ring is disposed on the die to surround the integrated circuit. The conductive layer at least covers the first region, and which is electrically connected to the seal ring.Type: ApplicationFiled: March 21, 2018Publication date: September 5, 2019Inventors: Chun Chiang, Ying-Wei Tseng, Ping-Chen Chang, Tien-Hao Tang
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Publication number: 20190229531Abstract: An electrostatic discharge (ESD) protection circuit has a first power node, a second power node, an ESD detect circuit, an ESD device and a voltage controlled switch. The ESD detect circuit is coupled between the first power node and the second power node for detecting an ESD current to output a control signal at a output terminal of the ESD detect circuit. The ESD device is coupled between the first power node and the second power node for leaking the ESD current. The voltage controlled switch is used to couple a body of the ESD device to the second power node according to at least a voltage level of the control signal.Type: ApplicationFiled: January 24, 2018Publication date: July 25, 2019Inventors: Yu-Cheng Liao, Ting-Yao Lin, Ping-Chen Chang, Tien-Hao Tang
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Publication number: 20180269198Abstract: An electrostatic discharge (ESD) protection device includes a substrate, a first gate group and a second gate group on the substrate, a drain region and a fourth doped region respectively at two sides of the first gate group, a source region and the fourth doped region respectively at two sides of the second gate group, a first doped region in the substrate and surrounded by the drain region, and a second doped region in the substrate and surrounded by the fourth doped region. The drain region and the source region have a first conductivity type. The first doped region and the second doped region have a second conductivity type complementary to the first conductivity type. The drain region is electrically connected to an input/output pad. The source region is electrically connected to a ground pad. The first doped region and the second doped region are electrically connected to each other.Type: ApplicationFiled: May 18, 2018Publication date: September 20, 2018Inventors: Chung-Yu Huang, Kuan-Cheng Su, Tien-Hao Tang, Ping-Chen Chang
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Patent number: 10008489Abstract: An electrostatic discharge protection semiconductor device includes a substrate, a gate set positioned on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, at least a first doped region formed in the drain region, and at least a second doped region formed in the substrate. The source region and the drain region include a first conductivity type, the first doped region and the second doped region include a second conductivity type, and the first conductivity and the second conductivity type are complementary to each other. The first doped region and the second doped region are electrically connected to each other.Type: GrantFiled: May 29, 2015Date of Patent: June 26, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Yu Huang, Kuan-Cheng Su, Tien-Hao Tang, Ping-Chen Chang
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Patent number: 10008492Abstract: An electrostatic discharge (ESD) device includes a gate structure, disposed on a substrate. A drain doped region of a first conductive type is in the substrate, adjacent to a first side of the gate structure, wherein the drain doped region has a first impurity concentration. A first doped region of the first conductive type is disposed within the drain doped region and being at least distant from the gate structure by a distance. The first doped region has a second impurity concentration lower than the first impurity concentration.Type: GrantFiled: November 16, 2016Date of Patent: June 26, 2018Assignee: United Microelectronics Corp.Inventors: Chung-Yu Huang, Ping-Chen Chang, Hou-Jen Chiu
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Publication number: 20180138167Abstract: An electrostatic discharge (ESD) device includes a gate structure, disposed on a substrate. A drain doped region of a first conductive type is in the substrate, adjacent to a first side of the gate structure, wherein the drain doped region has a first impurity concentration. A first doped region of the first conductive type is disposed within the drain doped region and being at least distant from the gate structure by a distance. The first doped region has a second impurity concentration lower than the first impurity concentration.Type: ApplicationFiled: November 16, 2016Publication date: May 17, 2018Applicant: United Microelectronics Corp.Inventors: Chung-Yu Huang, Ping-Chen Chang, Hou-Jen Chiu
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Patent number: 9899369Abstract: A layout structure is provided. The layout structure includes a substrate, a gate conductive layer, a first doped region having a first conductivity, a second doped region having the first conductivity, and a third doped region having a second conductivity. The gate conductive layer is formed on the substrate. The first doped region the second doped region are formed in the substrate and located at two sides of the gate conductive layer. The third doped region is formed in the substrate and adjacent to the second doped region. The third doped region and the second doped region form a diode. The gate conductive layer, the first doped region, and the third doped region are connected to ground, and the second doped region is connected to an input/output pad.Type: GrantFiled: September 22, 2015Date of Patent: February 20, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Pei-Shan Tseng, Yu-Cheng Liao, Ping-Chen Chang, Tien-Hao Tang, Kuan-Cheng Su
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Patent number: 9748222Abstract: A fin type ESD protection device includes at least one first fin, at least one second fin, and at least one gate structure. The first fin is disposed on a semiconductor substrate, and a source contact contacts the first fin. The second fin is disposed on the semiconductor substrate, and a drain contact contacts the second fin. The first fin and the second fin extend in a first direction respectively, and the first fin is separated from the second fin. The gate structure is disposed between the source contact and the drain contact. The first fin is separated from the drain contact, and the second fin is separated from the source contact.Type: GrantFiled: May 3, 2016Date of Patent: August 29, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Chun Chen, Ping-Chen Chang, Tien-Hao Tang, Kuan-Cheng Su
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Publication number: 20170084604Abstract: A layout structure is provided. The layout structure includes a substrate, a gate conductive layer, a first doped region having a first conductivity, a second doped region having the first conductivity, and a third doped region having a second conductivity. The gate conductive layer is formed on the substrate. The first doped region the second doped region are formed in the substrate and located at two sides of the gate conductive layer. The third doped region is formed in the substrate and adjacent to the second doped region. The third doped region and the second doped region form a diode. The gate conductive layer, the first doped region, and the third doped region are connected to ground, and the second doped region is connected to an input/output pad.Type: ApplicationFiled: September 22, 2015Publication date: March 23, 2017Inventors: Pei-Shan Tseng, Yu-Cheng Liao, Ping-Chen Chang, Tien-Hao Tang, Kuan-Cheng Su