Patents by Inventor Ping-Cheng Hsu
Ping-Cheng Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088246Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.Type: ApplicationFiled: November 16, 2023Publication date: March 14, 2024Inventors: Yu-Ling Hsu, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Wen-Tuo Huang, Yong-Shiuan Tsair, Chia-Sheng Lin, Shih Kuang Yang
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Publication number: 20240077804Abstract: A method includes forming a test pattern and a reference pattern in an absorption layer of a photomask structure. The test pattern has a first trench and a second trench, the reference pattern has a third trench and a fourth trench, the test pattern and the reference pattern have substantially the same dimension in a top view, and the second trench is deeper than the first trench, the third trench, and the fourth trench. The method further includes emitting a light beam to the test pattern to obtain a first interference pattern reflected from the test pattern, emitting the light beam to the reference pattern to obtain a second interference pattern reflected from the reference pattern; and comparing the first interference pattern with the second interference pattern to obtain a measured complex refractive index of the absorption layer.Type: ApplicationFiled: September 1, 2022Publication date: March 7, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ping-Hsun LIN, Chien-Cheng CHEN, Shih Ju HUANG, Pei-Cheng HSU, Ta-Cheng LIEN, Hsin-Chang LEE
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Patent number: 11800702Abstract: A method for forming a memory device includes the steps of providing a substrate, forming an isolation structure in the substrate to define a plurality of active regions in the substrate, the active regions respectively comprising two terminal portions and a central portion between the terminal portions, forming a plurality of island features on the substrate, wherein each of the island features covers two of the terminals portions respectively belonging to two of the active regions, performing a first etching process, using the island features as an etching mask to etch the substrate to define a plurality of island structures and a first recessed region surrounding the island structures on the substrate, and removing the island features to expose the island structures.Type: GrantFiled: March 16, 2021Date of Patent: October 24, 2023Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Hsu-Yang Wang, Ping-Cheng Hsu, Shih-Fang Tzou, Chin-Lung Lin, Yi-Hsiu Lee, Koji Taniguchi, Harn-Jiunn Wang, Tsung-Ying Tsai
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Patent number: 11665888Abstract: A method for fabricating semiconductor device includes the steps of: forming a semiconductor layer on a substrate; removing part of the semiconductor layer and part of the substrate to form a trench; forming a liner in the trench; removing part of the liner to form a spacer adjacent to two sides of the trench; forming a conductive layer in the trench; forming a metal layer on the conductive layer; forming a mask layer on the metal layer; and patterning the mask layer, the metal layer, and the conductive layer to form a bit line structure.Type: GrantFiled: December 25, 2020Date of Patent: May 30, 2023Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Wei-Lun Hsu, Hung-Lin Shih, Che-Hung Huang, Ping-Cheng Hsu, Hsu-Yang Wang
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Publication number: 20220238532Abstract: A DRAM capacitor may include a first capacitor electrode, a capacitor dielectric adjacent to the first capacitor electrode, and a second capacitor electrode adjacent to the capacitor dielectric. The first capacitor electrode may include a lower portion, an upper portion, and a step transition between the lower portion and the upper portion, a width of the upper portion of the first capacitor electrode at the step transition is less than a width of the lower portion of the first capacitor electrode at the step transition. Semiconductor devices, systems, and methods are also disclosed.Type: ApplicationFiled: January 13, 2022Publication date: July 28, 2022Inventors: Devesh Dadhich Shreeram, Kangle Li, Matthew N. Rocklein, Wei Ching Huang, Ping-Cheng Hsu, Sevim Korkmaz, Sanjeev Sapra, An-Jen B. Cheng
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Publication number: 20210202492Abstract: A method for forming a memory device includes the steps of providing a substrate, forming an isolation structure in the substrate to define a plurality of active regions in the substrate, the active regions respectively comprising two terminal portions and a central portion between the terminal portions, forming a plurality of island features on the substrate, wherein each of the island features covers two of the terminals portions respectively belonging to two of the active regions, performing a first etching process, using the island features as an etching mask to etch the substrate to define a plurality of island structures and a first recessed region surrounding the island structures on the substrate, and removing the island features to expose the island structures.Type: ApplicationFiled: March 16, 2021Publication date: July 1, 2021Inventors: Hsu-Yang Wang, Ping-Cheng Hsu, Shih-Fang Tzou, Chin-Lung Lin, Yi-Hsiu Lee, Koji Taniguchi, Harn-Jiunn Wang, Tsung-Ying Tsai
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Publication number: 20210118889Abstract: A method for fabricating semiconductor device includes the steps of: forming a semiconductor layer on a substrate; removing part of the semiconductor layer and part of the substrate to form a trench; forming a liner in the trench; removing part of the liner to form a spacer adjacent to two sides of the trench; forming a conductive layer in the trench; forming a metal layer on the conductive layer; forming a mask layer on the metal layer; and patterning the mask layer, the metal layer, and the conductive layer to form a bit line structure.Type: ApplicationFiled: December 25, 2020Publication date: April 22, 2021Inventors: Wei-Lun Hsu, Hung-Lin Shih, Che-Hung Huang, Ping-Cheng Hsu, Hsu-Yang Wang
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Patent number: 10985166Abstract: A method for forming a memory device is disclosed, including providing a substrate, forming an isolation structure and plural active regions in the substrate, forming a plurality of island features on the substrate respectively covering two of the terminal portions of the active regions, using the island features as an etching mask to etch the substrate to perform a first etching process to define a first recessed region and plural island structures on the substrate. The island structures respectively comprise the two terminal portions of the active regions and the first recessed region comprises the central portions of the active regions.Type: GrantFiled: October 31, 2018Date of Patent: April 20, 2021Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Hsu-Yang Wang, Ping-Cheng Hsu, Shih-Fang Tzou, Chin-Lung Lin, Yi-Hsiu Lee, Koji Taniguchi, Harn-Jiunn Wang, Tsung-Ying Tsai
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Patent number: 10910386Abstract: According to an embodiment of the present invention, a method for fabricating semiconductor device includes the steps of: forming a semiconductor layer on a substrate; removing part of the semiconductor layer and part of the substrate to form a trench; forming a liner in the trench; removing part of the liner to form a spacer adjacent to two sides of the trench; and forming a bit line structure in the trench.Type: GrantFiled: April 3, 2018Date of Patent: February 2, 2021Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Wei-Lun Hsu, Hung-Lin Shih, Che-Hung Huang, Ping-Cheng Hsu, Hsu-Yang Wang
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Publication number: 20190279989Abstract: According to an embodiment of the present invention, a method for fabricating semiconductor device includes the steps of: forming a semiconductor layer on a substrate; removing part of the semiconductor layer and part of the substrate to form a trench; forming a liner in the trench; removing part of the liner to form a spacer adjacent to two sides of the trench; and forming a bit line structure in the trench.Type: ApplicationFiled: April 3, 2018Publication date: September 12, 2019Inventors: Wei-Lun Hsu, Hung-Lin Shih, Che-Hung Huang, Ping-Cheng Hsu, Hsu-Yang Wang
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Publication number: 20190189620Abstract: A method for forming a memory device is disclosed, including providing a substrate, forming an isolation structure and plural active regions in the substrate, forming a plurality of island features on the substrate respectively covering two of the terminal portions of the active regions, using the island features as an etching mask to etch the substrate to perform a first etching process to define a first recessed region and plural island structures on the substrate. The island structures respectively comprise the two terminal portions of the active regions and the first recessed region comprises the central portions of the active regions.Type: ApplicationFiled: October 31, 2018Publication date: June 20, 2019Inventors: Hsu-Yang Wang, Ping-Cheng Hsu, Shih-Fang Tzou, Chin-Lung Lin, Yi-Hsiu Lee, Koji Taniguchi, Harn-Jiunn Wang, Tsung-Ying Tsai
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Patent number: 8658538Abstract: A method of fabricating a memory device includes forming a plurality of first insulative blocks and a plurality of second insulative blocks arranged in an alternating manner in a substrate, forming a plurality of wide trenches in the substrate to form a plurality of protruding blocks, forming a word line on each sidewall of the protruding blocks, isolating the word line on each sidewall of the protruding block, and forming an trench filler in the protruding block to form two mesa structures, wherein the first insulative block and the second insulative block have different depths, and the wide trenches are transverse to the first insulative blocks.Type: GrantFiled: March 7, 2013Date of Patent: February 25, 2014Assignee: Nanya Technology CorporationInventors: Ying Cheng Chuang, Ping Cheng Hsu, Sheng Wei Yang, Ming Cheng Chang, Hung Ming Tsai
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Patent number: 8647988Abstract: A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections.Type: GrantFiled: March 4, 2013Date of Patent: February 11, 2014Assignee: Nanya Technology CorporationInventors: Ying Cheng Chuang, Ping Cheng Hsu, Sheng Wei Yang, Ming Cheng Chang, Hung Ming Tsai
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Patent number: 8426925Abstract: A memory device includes a plurality of isolations and trench fillers arranged in an alternating manner in a direction, a plurality of mesa structures between the isolations and trench fillers, and a plurality of word lines each overlying a side surface of the respective mesa. In one embodiment of the present invention, the width measured in the direction of the trench filler is smaller than that of the isolation, each mesa structure includes at least one paired source/drain regions and at least one channel base region corresponding to the paired source/drain regions, and each of the word lines is on a side surface of the mesa structure, adjacent the respective isolation, and is arranged adjacent the channel base region.Type: GrantFiled: November 12, 2010Date of Patent: April 23, 2013Assignee: Nanya Technology Corp.Inventors: Ying Cheng Chuang, Ping Cheng Hsu, Sheng Wei Yang, Ming Cheng Chang, Hung Ming Tsai
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Patent number: 8415728Abstract: A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections.Type: GrantFiled: November 12, 2010Date of Patent: April 9, 2013Assignee: Nanya Technology Corp.Inventors: Ying Cheng Chuang, Ping Cheng Hsu, Sheng Wei Yang, Ming Cheng Chang, Hung Ming Tsai
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Patent number: 8334196Abstract: A method of forming a conductive contact includes forming a structure comprising an upper surface joining with a sidewall surface. The sidewall surface contains elemental-form silicon. Silicon is epitaxially grown from the sidewall surface. Dielectric material is formed over the upper surface and the epitaxially-grown silicon. A conductive contact is formed through the dielectric material to conductively connect with the upper surface.Type: GrantFiled: November 1, 2010Date of Patent: December 18, 2012Assignee: Micron Technology, Inc.Inventors: Ying-Cheng Chuang, Hung-Ming Tsai, Sheng-Wei Yang, Ping-Cheng Hsu, Ming-Cheng Chang
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Publication number: 20120119277Abstract: A memory device includes a plurality of isolations and trench fillers arranged in an alternating manner in a direction, a plurality of mesa structures between the isolations and trench fillers, and a plurality of word lines each overlying a side surface of the respective mesa. In one embodiment of the present invention, the width measured in the direction of the trench filler is smaller than that of the isolation, each mesa structure includes at least one paired source/drain regions and at least one channel base region corresponding to the paired source/drain regions, and each of the word lines is on a side surface of the mesa structure, adjacent the respective isolation, and is arranged adjacent the channel base region.Type: ApplicationFiled: November 12, 2010Publication date: May 17, 2012Applicant: NANYA TECHNOLOGY CORP.Inventors: YING CHENG CHUANG, PING CHENG HSU, SHENG WEI YANG, MING CHENG CHANG, HUNG MING TSAI
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Publication number: 20120119276Abstract: A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections.Type: ApplicationFiled: November 12, 2010Publication date: May 17, 2012Applicant: NANYA TECHNOLOGY CORP.Inventors: YING CHENG CHUANG, PING CHENG HSU, SHENG WEI YANG, MING CHENG CHANG, HUNG MING TSAI
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Publication number: 20120108047Abstract: A method of forming a conductive contact includes forming a structure comprising an upper surface joining with a sidewall surface. The sidewall surface contains elemental-form silicon. Silicon is epitaxially grown from the sidewall surface. Dielectric material is formed over the upper surface and the epitaxially-grown silicon. A conductive contact is formed through the dielectric material to conductively connect with the upper surface.Type: ApplicationFiled: November 1, 2010Publication date: May 3, 2012Inventors: Ying-Cheng Chuang, Hung-Ming Tsai, Sheng-Wei Yang, Ping-Cheng Hsu, Ming-Cheng Chang