Patents by Inventor Ping-Chieh Chiang

Ping-Chieh Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240179894
    Abstract: Methods, apparatuses, and systems related to a metal sense line contact are described. An example apparatus includes a sense line pillar comprising a barrier material over a semiconductor substrate. The sense line pillar further includes a liner material adjacent the barrier material. The sense line pillar further includes a first metal material over the barrier material. The sense line pillar further includes a second metal material over the first metal material. The sense line pillar further includes a cap material over the second metal material. The apparatus further cell contacts between a plurality of sense line pillars.
    Type: Application
    Filed: November 1, 2023
    Publication date: May 30, 2024
    Inventor: Ping Chieh Chiang
  • Publication number: 20240038588
    Abstract: A method of forming a microelectronic device comprises forming interlayer dielectric material over a base structure comprising semiconductive structures separated from one another by insulative structures. Sacrificial line structures separated from one another by trenches are formed over the interlayer dielectric material. The sacrificial line structures horizontally overlap some of the semiconductive structures, and the trenches horizontally overlap some other of the semiconductive structures. Plug structures are formed within horizontal areas of the trenches and extend through the interlayer dielectric material and into the some other of the semiconductive structures. The sacrificial line structures are replaced with additional trenches. Conductive contact structures are formed within horizontal areas of the additional trenches and extend through the interlayer dielectric material and into the some of the semiconductive structures.
    Type: Application
    Filed: July 27, 2022
    Publication date: February 1, 2024
    Inventors: Terrence B. McDaniel, Vinay Nair, Russell A. Benson, Christopher W. Petz, Si-Woo Lee, Silvia Borsari, Ping Chieh Chiang, Luca Fumagalli
  • Publication number: 20230062092
    Abstract: A recessed access device comprises a conductive gate in a trench in semiconductor material. A gate insulator extends along sidewalls and around a bottom of the conductive gate between the conductive gate and the semiconductor material. A pair of source/drain regions are in upper portions of the semiconductor material on opposing lateral sides of the trench. A channel region in the semiconductor material below the pair of source/drain regions extends along sidewalls and around a bottom of the trench. The gate insulator comprises a low-k material and a high-k material. The low-k material is characterized by its dielectric constant k being no greater than 4.0. The high-k material is both (a) and (b), where: (a): characterized by its dielectric constant k being greater than 4.0; and (b): comprising SixMyO, where “M” is one or more of Al, metal(s) from Group 2, Group 3, Group 4, Group 5, and the lanthanide series of the periodic table; “x” is 0.999 to 0.6; and “y” is 0.001 to 0.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Hyuck Soo Yang, Sau Ha Cheung, Richard Beeler, Ping Chieh Chiang, Hyoung Lee, Jaydip Guha, Soichi Sugiura
  • Publication number: 20220375942
    Abstract: A microelectronic device comprises memory cell structures extending from a base material. At least one memory cell structure of the memory cell structures comprises a central portion in contact with a digit line, extending from the base material and comprising opposing arcuate surfaces, an end portion in contact with a storage node contact on a side of the central portion, and an additional end portion in contact with an additional storage node contact on an opposite side of the central portion. Related microelectronic devices, electronic systems, and methods are also described.
    Type: Application
    Filed: May 18, 2021
    Publication date: November 24, 2022
    Inventors: Stephen D. Snyder, Thomas A. Figura, Siva Naga Sandeep Chalamalasetty, Ping Chieh Chiang, Scott L. Light, Yashvi Singh, Yan Li, Song Guo
  • Publication number: 20140042548
    Abstract: A DRAM structure with buried word lines is described, including a semiconductor substrate, cell word lines buried in the substrate and separated from the same by a first gate dielectric layer, and isolation word lines buried in the substrate and separated from the same by a second gate dielectric layer. The top surfaces of the cell word lines and those of the isolation word lines are lower than the top surface of the substrate. The bottom surfaces of the isolation word lines are lower than those of the cell word lines.
    Type: Application
    Filed: October 7, 2013
    Publication date: February 13, 2014
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Hao-Chieh Liu, Lars Heineck, Ping-Chieh Chiang
  • Publication number: 20120292716
    Abstract: A DRAM structure with buried word lines is described, including a semiconductor substrate, cell word lines buried in the substrate and separated from the same by a first gate dielectric layer, and isolation word lines buried in the substrate and separated from the same by a second gate dielectric layer. The top surfaces of the cell word lines and those of the isolation word lines are lower than the top surface of the substrate. The bottom surfaces of the isolation word lines are lower than those of the cell word lines.
    Type: Application
    Filed: May 17, 2011
    Publication date: November 22, 2012
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Hao-Chieh Liu, Lars Heineck, Ping-Chieh Chiang