Patents by Inventor Ping-Chih Chang

Ping-Chih Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090065811
    Abstract: A semiconductor device with ohmic contact is provided with a method of making the same. In one embodiment, a method is provided for fabricating a semiconductor device. The method comprises providing a semiconductor structure with a N-type doped semiconductor contact layer, forming a platinum contact portion over the N-type doped semiconductor contact layer, forming an adhesive contact portion over the platinum contact portion, forming a barrier contact portion over the adhesive contact portion, and forming a gold contact portion over the barrier contact portion. The method further comprises annealing the semiconductor structure to alloy the platinum contact portion with the N-type doped semiconductor contact layer to form a platinum/semiconductor alloyed diffusion contact barrier substantially disposed within the N-type doped semiconductor contact layer.
    Type: Application
    Filed: September 7, 2007
    Publication date: March 12, 2009
    Inventors: Ping-Chih Chang, Xiaobing Mei, Augusto Gutierrez-Aitken
  • Publication number: 20080258242
    Abstract: A semiconductor device (100) is formed on a semi-insulating semiconductor substrate (101) including a channel layer (104), a spacer layer (105), an electron supply layer (106), and a barrier layer (108). A composite layer (110) is formed over the barrier layer (108). A metal (116) is deposited over the composite layer (110). The metal (116) is annealed to promote a chemical reaction between the metal (116) and the composite layer (110) in which a portion of the metal sinks into the composite layer (110) and forms an ohmic contact with the composite layer.
    Type: Application
    Filed: April 19, 2007
    Publication date: October 23, 2008
    Applicant: Northrop Grumman Space and Mission Systems Corp.
    Inventors: Xiaobing Mei, Ping-Chih Chang, Michael David Lange
  • Patent number: 6765242
    Abstract: An NPN double heterostructure bipolar transistor (DHBT) is disclosed with a base region comprising a layer of p-type-doped indium gallium arsenide nitride (InGaAsN) sandwiched between n-type-doped collector and emitter regions. The use of InGaAsN for the base region lowers the transistor turn-on voltage, Von, thereby reducing power dissipation within the device. The NPN transistor, which has applications for forming low-power electronic circuitry, is formed on a gallium arsenide (GaAs) substrate and can be fabricated at commercial GaAs foundries. Methods for fabricating the NPN transistor are also disclosed.
    Type: Grant
    Filed: April 11, 2000
    Date of Patent: July 20, 2004
    Assignees: Sandia Corporation, Emcore Corporation
    Inventors: Ping-Chih Chang, Albert G. Baca, Nein-Yi Li, Hong Q. Hou, Carol I. H. Ashby