Abstract: An integrated circuit (IC) is provided. The IC includes an RF transmitter and an RF receiver. The RF transmitter is configured to generate an RF signal in response to an analog test signal from a test signal generator of a module circuitry that is external to the IC. The RF receiver is configured to generate an outgoing signal according to an input RF signal, and to report the outgoing signal to the module circuitry. The module circuitry performs a test analysis on the RF signal generated by the RF transmitter or on the outgoing signal generated by the RF receiver to determine a test result. The test result is reported to a test equipment having no RF instruments.

Abstract: An integrated circuit (IC) is provided. The IC includes an RF transmitter and an RF receiver. The RF transmitter is configured to generate an RF signal in response to an analog test signal from a test signal generator of a module circuitry that is external to the IC. The RF receiver is configured to generate an outgoing signal according to an input RF signal, and to report the outgoing signal to the module circuitry. The module circuitry performs a test analysis on the RF signal generated by the RF transmitter or on the outgoing signal generated by the RF receiver to determine a test result. The test result is reported to a test equipment having no RF instruments.

Abstract: A GNSS receiver having an IF process engine is disclosed. The IF process engine provides a plurality of carriers with different frequencies and down converts IF signals into baseband signals by using the carriers in a time division multiplex (TDM) schedule. The IF process engine has a local oscillator part for generating the carriers with different frequencies; an IF down-converter for respectively mixing the IF signal with the carriers generated by the local oscillator part to generate IF removed signal segments; a time division multiplex (TDM) controller for scheduling the respective mixing operations of the IF down-converter for the IF signal with the respective carriers; and a buffer for storing the IF removed signal segments generated by the IF down-converter.

Abstract: An IC, a circuitry, and an RF BIST system are provided. The RF BIST system includes a test equipment, a module circuitry, and an IC. The IC is arranged to communicate with the module circuitry by an RF signal in response to a command signal from the test equipment, determine a test result by the RF signal, and report the test result to the test equipment, wherein the module circuitry is external to the IC and the test equipment.

Abstract: An IC, a circuitry, and an RF BIST system are provided. The RF BIST system includes a test equipment, a module circuitry, and an IC. The IC is arranged to communicate with the module circuitry by an RF signal in response to a command signal from the test equipment, determine a test result by the RF signal, and report the test result to the test equipment, wherein the module circuitry is external to the IC and the test equipment.

Abstract: The invention provides a code memory capable of code provision for a plurality of physical channels. In one embodiment, the code memory comprises a selecting multiplexer, a core memory module, and a code buffer. The selecting multiplexer repeatedly latches on to a plurality of addresses generated by the physical channels according to a sequence of the physical channels to generate a code memory address signal. The core memory module stores code data, and retrieves the code data according to the code memory address signal to generate a code memory data signal. The code buffer respectively retrieves a plurality of code segments requested by the physical channels from the code memory data signal according to the sequence of the physical channels, and stores the code segments.

Abstract: The invention provides a memory code generator. In one embodiment, the memory code generator comprises a code memory, a preparation buffer set, and a correlation buffer set. The code memory stores code data. The preparation buffer set retrieves a first code segment of the code data from the code memory, and shifts the first code segment to obtain a second code segment with a desired code phase required by the correlation buffer set. The correlation buffer set loads the second code segment from the preparation buffer set, and provides a correlation code for correlation according to the second code segment. The preparation buffer set prepares the second code segment corresponding to a subsequent correlation when the correlation buffer set is providing the correlation code for a current correlation according to the first code segment.

Abstract: The invention provides a code memory capable of code provision for a plurality of physical channels. In one embodiment, the code memory comprises a selecting multiplexer, a core memory module, and a code buffer. The selecting multiplexer repeatedly latches on to a plurality of addresses generated by the physical channels according to a sequence of the physical channels to generate a code memory address signal. The core memory module stores code data, and retrieves the code data according to the code memory address signal to generate a code memory data signal. The code buffer respectively retrieves a plurality of code segments requested by the physical channels from the code memory data signal according to the sequence of the physical channels, and stores the code segments.

Abstract: The invention provides a memory code generator. In one embodiment, the memory code generator comprises a code memory, a preparation buffer set, and a correlation buffer set. The code memory stores code data. The preparation buffer set retrieves a first code segment of the code data from the code memory, and shifts the first code segment to obtain a second code segment with a desired code phase required by the correlation buffer set. The correlation buffer set loads the second code segment from the preparation buffer set, and provides a correlation code for correlation according to the second code segment. The preparation buffer set prepares the second code segment corresponding to a subsequent correlation when the correlation buffer set is providing the correlation code for a current correlation according to the first code segment.

Abstract: A GNSS receiver having an IF process engine is disclosed. The IF process engine provides a plurality of carriers with different frequencies and down converts IF signals into baseband signals by using the carriers in a time division multiplex (TDM) schedule. The IF process engine has a local oscillator part for generating the carriers with different frequencies; an IF down-converter for respectively mixing the IF signal with the carriers generated by the local oscillator part to generate IF removed signal segments; a time division multiplex (TDM) controller for scheduling the respective mixing operations of the IF down-converter for the IF signal with the respective carriers; and a buffer for storing the IF removed signal segments generated by the IF down-converter.