Patents by Inventor Ping Keung Ko

Ping Keung Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6300649
    Abstract: An SOI MOSFET having improved electrical characteristics includes a low barrier body contact under the source region, and alternatively under the drain region, to facilitate collection and removal of current carriers generated by impact ionization. Fully-depleted and non-fully-depleted SOI MOSFETs can be integrated on the same chip by providing some transistors with thicker source and drain regions with a recessed channel therebetween and by selective channel dopant implant. Accordingly, digital circuitry and analog circuitry can be combined on one substrate. Improved electrostatic discharge protection is provided by fabricating transistors for the protection circuit directly in the supporting substrate by first removing the silicon thin film and underlying insulation barrier.
    Type: Grant
    Filed: August 4, 2000
    Date of Patent: October 9, 2001
    Assignee: The Regents of the University of California
    Inventors: Chenming Hu, Mansun John Chan, Hsing-Jen Wann, Ping Keung Ko
  • Patent number: 6121077
    Abstract: An SOI MOSFET having improved electrical characteristics includes a low barrier body contact under the source region, and alternatively under the drain region, to facilitate collection and removal of current carriers generated by impact ionization. Fully-depleted and non-fully-depleted SOI MOSFETs can be integrated on the same chip by providing some transistors with thicker source and drain regions with a recessed channel therebetween and by selective channel dopant implant. Accordingly, digital circuitry and analog circuitry can be combined on one substrate. Improved electrostatic discharge protection is provided by fabricating transistors for the protection circuit directly in the supporting substrate by first removing the silicon thin film and underlying insulation barrier.
    Type: Grant
    Filed: September 10, 1999
    Date of Patent: September 19, 2000
    Assignee: The Regents of the University of California
    Inventors: Chenming Hu, Mansun John Chan, Hsing-Jen Wann, Ping Keung Ko
  • Patent number: 5982003
    Abstract: An SOI MOSFET having improved electrical characteristics includes a low barrier body contact under the source region, and alternatively under the drain region, to facilitate collection and removal of current carriers generated by impact ionization. Fully-depleted and non-fully-depleted SOI MOSFETs can be integrated on the same chip by providing some transistors with thicker source and drain regions with a recessed channel therebetween and by selective channel dopant implant. Accordingly, digital circuitry and analog circuitry can be combined on one substrate. Improved electrostatic discharge protection is provided by fabricating transistors for the protection circuit directly in the supporting substrate by first removing the silicon thin film and underlying insulation barrier.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: November 9, 1999
    Assignee: The Regents of the University of California
    Inventors: Chenming Hu, Mansun John Chan, Hsing-Jen Wann, Ping Keung Ko
  • Patent number: 5790436
    Abstract: A system and method of simulating operation of an integrated circuit. First, circuit characteristics of circuit components are measured, and a set of circuit simulation model parameters are generated for each measured circuit component. Then, the operation of predefined circuit primitives is simulated using each of the generated sets of circuit simulation model parameters. The circuit primitives include the measured circuit components. The simulated operations are then analyzed to select ones of the simulated operations that are worst, best and nominal with respect to a specified circuit performance parameter and to extract model parameters corresponding to the worst case, best case and nominal case sets of circuit simulation model parameters from the generated sets of circuit simulation model parameters. Each extracted set of circuit simulation model parameters comprises one of the generated sets of circuit simulation model parameters.
    Type: Grant
    Filed: November 3, 1997
    Date of Patent: August 4, 1998
    Assignee: BTA Technology, Inc.
    Inventors: James Chieh-Tsung Chen, Zhihong Liu, Chenming Hu, Ping Keung Ko