Abstract: A floating point pre-alignment structure for computing-in-memory applications includes a time domain exponent computing block and an input mantissa pre-align block. The time domain exponent computing block is configured to compute a plurality of original input exponents and a plurality of original weight exponents to generate a plurality of flags. Each of the flags is determined by adding one of the original input exponents and one of the original weight exponents. The input mantissa pre-align block is configured to receive a plurality of original input mantissas and shift the original input mantissas according to the flags to generate a plurality of weighted input mantissas, and sparsity of the weighted input mantissas is greater than sparsity of the original input mantissas. Each of the flags has a negative correlation with a sum of the one of the original input exponents and the one of the original weight exponents.

Abstract: A memory unit with time domain edge delay accumulation for computing-in-memory applications is controlled by a first word line and a second word line. The memory unit includes at least one memory cell, at least one edge-delay cell multiplexor and at least one edge-delay cell. The at least one edge-delay cell includes a weight reader and a driver. The weight reader is configured to receive a weight and a multi-bit analog input voltage and generate a multi-bit voltage according to the weight and the multi-bit analog input voltage. The driver is connected to the weight reader and configured to receive an edge-input signal. The driver is configured to generate an edge-output signal having a delay time according to the edge-input signal and the multi-bit voltage. The delay time of the edge-output signal is positively correlated with the multi-bit analog input voltage multiplied by the weight.

Abstract: A federated learning method includes: providing importance parameters and performance parameters by client devices respectively to a central device, performing a training procedure by the central device, wherein the training procedure includes: selecting target devices from the client devices according to a priority order associated with the importance parameters, dividing the target devices into training groups according to a similarity of the performance parameters, notifying the target devices to perform iterations according to the training groups respectively to generate trained models, transmitting the trained models to the central device, and updating a global model based on the trained models, performing the training procedure again or outputting the global model to the client devices based on a convergence value of the global model and the number of times of performing the training procedure.

Abstract: A method of performing automatic tuning on a deep learning model includes: utilizing an instruction-based learned cost model to estimate a first type of operational performance metrics based on a tuned configuration of layer fusion and tensor tiling; utilizing statistical data gathered during a compilation process of the deep learning model to determine a second type of operational performance metrics based on the tuned configuration of layer fusion and tensor tiling; performing an auto-tuning process to obtain a plurality of optimal configurations based on the first type of operational performance metrics and the second type of operational performance metrics; and configure the deep learning model according to one of the plurality of optimal configurations.

Abstract: The dipole-resonator resistive absorber is a metamaterial absorber operating in the microwave regime. A single unit of the dipole-resonator resistive absorber includes a first rectangular conductive ring having a pair of first resistors mounted thereon and in electrical communication therewith, and a plurality of parallel linear arrays of second rectangular conductive rings, where each of the second rectangular conductive rings has a pair of second resistors mounted thereon and in electrical communication therewith. The first rectangular conductive ring is mounted above the plurality of parallel linear arrays of the second rectangular conductive rings, and this structure is backed by an electrically conductive layer. The single unit dipole-resonator resistive absorber may be expanded into an arrayed structure, forming a polarization-independent dipole-resonator resistive absorber.

Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.

Abstract: The present invention relates to a method of image fusion, which uses the brightness difference of the current frame and the previous frame to determine whether the pixel in a frame image is static or dynamic. If the current pixel is static, the previous corresponding pixel is superimposed onto the current pixel; if the current pixel is dynamic, the previous corresponding pixel is replaced with the current pixel.

Abstract: A system and computer-implemented method are provided for manufacturing a semiconductor electronic device. An assembler receives a jig and a boat supporting a die. The assembler includes a separator that separates the jig into a first jig portion and a second jig portion and a loader that positions the boat between the first jig portion and the second jig portion. A robot receives an assembly prepared by the assembler and manipulates a locking system that fixes an alignment of the boat relative to the first jig portion and the second jig portion to form a locked assembly. A process chamber receives the locked assembly and subjects the locked assembly to a fabrication operation.

Abstract: A soft boundary structure is implemented using a resonator structure capable of receiving sound or vibration, establishing resonance coupled with received sound or vibration, and creating a reflection with a pi phase factor. A soft boundary is located on or closely adjacent the resonator structure. The soft boundary cooperates with the resonator structure to attenuate the sound or vibration.

Abstract: A solid state device for a computer system is disclosed. The computer system includes a detecting module for detecting a connection state of a connector of a backplane of the computer system. The solid state device includes a memory module, configured to store data; a connection module, configured to connect the connector of the backplane of the computer system; and a controller module, coupled to the memory module and the connection module, configured to write data into the memory module according to a writing notification from the computer system when the connection state between the connection module and the connector of the computer system is changed from a first connection state to a second connection state, and to notify the computer system to unlock the connector of the computer system after finishing writing the data.

Abstract: The invention provides a reticle pod, in particular the reticle pod with wear parts. The reticle pod is a large-size reticle pod and includes a vertical accommodation space for accommodating reticles. The reticle pod mainly includes a cover and a box. The box is used to combine with the cover to form an internal space in order to accommodate reticles. Guiding members are disposed outside the box, and the guiding members can help guide the relative position of the box and the cover. The contact surfaces of the box contacting the upright reticles are disposed with at least two slots, and each of the slot is configured with at least one wear part. The wear part module further includes a first wear part disposed on the upper portion of the slot and a second wear part disposed on the lower portion of the slot.

Abstract: An ultra high molecular weight polyethylene (UHMWPE) membrane has at least one nanoporous UHMWPE film, where each of the nanoporous UHMWPE film is biaxial oriented with a thickness of 0.1 to 12 ?m and pores that exclude particles in excess of 10 nm with a total porosity of 65 to 75 percent. The nanoporous UHMWPE film can be coated or laminated by a hydrophilic polymer to form a Janus membrane and can be made with a multilayer composite structure. The UHMWPE membrane can be used in a device for molecular distillation (MD), reverse osmosis (RO), or forward osmosis (FO).

Abstract: A solid state device for a computer system is disclosed. The computer system includes a detecting module for detecting a connection state of a connector of a backplane of the computer system. The solid state device includes a memory module, configured to store data; a connection module, configured to connect the connector of the backplane of the computer system; and a controller module, coupled to the memory module and the connection module, configured to write data into the memory module according to a writing notification from the computer system when the connection state between the connection module and the connector of the computer system is changed from a first connection state to a second connection state, and to notify the computer system to unlock the connector of the computer system after finishing writing the data.

Abstract: A power device includes a power factor corrector, an auxiliary capacitor, a switching device, an auxiliary boost circuit, a controller and a voltage conversion device. The switching device has a first end electrically connected to the output end of the power factor corrector, and a second end electrically connected to one end of the auxiliary capacitor. An output end of the auxiliary boost circuit is electrically connected to the output end of the power factor corrector, an input end of the auxiliary boost circuit is electrically connected to a middle end of the switching device, and a ground end of the auxiliary boost circuit is electrically connected to another end of the auxiliary capacitor. The controller is electrically connected to the switching device and the auxiliary boost circuit. The input end of the voltage conversion device is electrically connected to the output end of the power factor corrector.

Abstract: A handle mechanism is to be mounted on a slidable plate and to slide the slidable plate relative to a chassis. The handle mechanism includes a handle and an engagement component. The handle is adapted to be pivotably disposed on the slidable plate so as to have an engaged position and a disengaged position. The engagement component is slidably disposed on the handle and adapted to contact the chassis to slide the slidable plate into the chassis. The engagement component has a contact surface, and the contact surface has an edge located away from an axis of the handle. A distance between the edge of the contact surface of the engagement component and the axis of the handle in the engaged position is smaller than a distance between the edge of the contact surface of the engagement component and the axis of the handle in the disengaged position.

Abstract: An information handling system includes a cooling fan operable in one of a plurality of fan speed levels, and a connector to which a headphone device can be connected. A mode controller sets the cooling fan to a first fan speed levels, receives an indication that the headphone device is connected to the connector, and sets the cooling fan in a second, higher fan speed level in response to receiving the indication.

Abstract: A testing apparatus including a testing platform, a loading device, a testing-signal generating device, a sound sensing device, a control unit, and an unloading device is disclosed. The loading device is configured to load a plurality of under-test devices to the testing platform. The testing-signal generating device is configured to generate at least one testing signal. The plurality of under-test devices receives the at least one testing signal and produces at least one testing sound-according to the at least one testing signal. The sound sensing device is configured to receive the at least one testing sound. The control unit controls the unloading device to unload the plurality of under-test devices from the testing platform and controls the unloading device to categorize the plurality of under-test devices into a plurality of groups according to the at least one testing sound received by the sound sensing device.

Abstract: A power device includes a power factor corrector, an auxiliary capacitor, a switching device, an auxiliary boost circuit, a controller and a voltage conversion device. The switching device has a first end electrically connected to the output end of the power factor corrector, and a second end electrically connected to one end of the auxiliary capacitor. An output end of the auxiliary boost circuit is electrically connected to the output end of the power factor corrector, an input end of the auxiliary boost circuit is electrically connected to a middle end of the switching device, and a ground end of the auxiliary boost circuit is electrically connected to another end of the auxiliary capacitor. The controller is electrically connected to the switching device and the auxiliary boost circuit. The input end of the voltage conversion device is electrically connected to the output end of the power factor corrector.

Abstract: Embodiments described herein provide for an emulation system that supports efficiently generating outgoing messages to a test bench. The emulation system transmits the outgoing messages to the test bench various busses and interfaces. The compiled virtual logic writes the outgoing messages into memories of the emulation chips for queuing, and notification messages associated with the queued outgoing messages. A traffic processor transfers from memories to the test bench using buses and interfaces. The traffic processor reads a notification message from memory to identify the storage location with a corresponding queued outgoing message. The traffic processor then transmits DMA requests to I/O components (e.g., DMA engines) to instruct the I/O components to transfer the queued outgoing message to the host device.