Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.

Abstract: A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a plurality of pads, a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A plurality of first openings of the first dielectric layer expose part of the pads, and a first surface of the first dielectric layer is higher upper surfaces of the pads. The solder balls are disposed in a plurality of third openings of the third dielectric layer and are electrically connected to the second metal layer and the carrier. The surface treatment layer is disposed on the upper surfaces, and a top surface of the surface treatment layer is higher than the first surface.

Abstract: A chip package includes a redistribution layer, a chip, and an encapsulation member. The redistribution layer includes an insulation part, a plurality of first pads and a plurality of second pads, where the insulation part has a first surface, a second surface opposite to the first surface, and a side surface between the first surface and the second surface. The first pads and the second pads are located at the first surface and the second surface respectively. The chip is disposed on the first surface and electrically connected to the first pads. The encapsulation member wraps the chip and the redistribution layer, and covers the first surface and the side surface, where the encapsulation member exposes the second pads, and the encapsulation member is not flush with the first surface and the side surface.