Abstract: The embodiments of the present application provide a radar-sensing detection method and device based on radar-sensing communication integration. Said method comprises: when being applied to a sending end, determining a position of a receiving end, then sending a beam control signal to the receiving end through a preset beam control request channel, receiving a beam control response signal sent by the receiving end, and sending a first detection result signal to the receiving end in a preset reservation channel. The embodiments of the present application can expand the detection range of an autonomous vehicle.

Abstract: An aspect of the disclosure includes a communication system and a communication method using reconfigurable intelligent surface and a reconfigurable intelligent surface device. The communication system includes at least one base station, a reconfigurable intelligent surface device, and a control at one least device. The at least one base station respectively transmits at least one beam. The reconfigurable intelligent surface device is coupled to the at least one base station, and measures the at least one beam of the at least one base station to obtain signal measurement results associated with each of the at least one base station. The control device is coupled to the at least one base station. The control device groups the at least one base station and the reconfigurable intelligent surface device into at least one group according to the signal measurement results associated with each of the at least one base station.

Abstract: A semiconductor structure is provided, including: a substrate and a dielectric layer arranged on the substrate; a conductive plug, wherein a first part of the conductive plug is arranged in the substrate, and a second part of the conductive plug is arranged in the dielectric layer; and an isolation ring structure at least surrounding the second part of the conductive plug.

Abstract: An electrostatic discharge device including at least two conductive materials isolated from each other and at least one electrostatic eliminator. The conductive materials are located outside two opposite side walls of an insulated fluid-carrying member and separated from the side walls thereof. When electrostatic charges are accumulated on the insulated fluid-carrying member, the electrostatic charges form an electrostatic voltage on the conductive materials. The electrostatic eliminator is electrically connected to the conductive materials and directly disconnected from a grounding terminal. The electrostatic eliminator releases and eliminates the electrostatic charges by the conductive materials to reduce the electrostatic voltage. In addition, the insulated fluid-carrying member can also be replaced by an insulation container. When the insulation container is used, induction electrodes can replace the conductive materials in the insulation container.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip (IC). The method includes forming a first fin of semiconductor material and a second fin of semiconductor material within a semiconductor substrate. A gate structure is formed over the first fin and source/drain regions are formed on or within the first fin. The source/drain regions are formed on opposite sides of the gate structure. One or more pick-up regions are formed on or within the second fin. The source/drain regions respectively have a first width measured along a first direction parallel to a long axis of the first fin and the one or more pick-up regions respectively have a second width measured along the first direction. The second width is larger than the first width.

Abstract: A method includes forming a first fin and a second fin protruding from a frontside of a substrate, forming a gate stack over the first and second fins, forming a dielectric feature dividing the gate stack into a first segment engaging the first fin and a second segment engaging the second fin, and growing a first epitaxial feature on the first fin and a second epitaxial feature on the second fin. The dielectric feature is disposed between the first and second epitaxial features. The method also includes performing an etching process on a backside of the substrate to form a backside trench, and forming a backside via in the backside trench. The backside trench exposes the dielectric feature and the first and second epitaxial features. The backside via straddles the dielectric feature and is in electrical connection with the first and second epitaxial features.

Abstract: A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.

Abstract: A method includes bonding a first package and a second package over a package component, adhering a first Thermal Interface Material (TIM) and a second TIM over the first package and the second package, respectively, dispensing an adhesive feature on the package component, and placing a heat sink over and contacting the adhesive feature. The heat sink includes a portion over the first TIM and the second TIM. The adhesive feature is then cured.

Abstract: The present application disclosures a double production line and a rapid prefabrication process of a segmental beam. The double production line including two production machine and a track system provided on the construction ground; the production machine includes a fixed end mold, two side molds, a bottom mold trolley, a middle internal mold trolley and two side internal mold trolley; two side molds are positioned on two sides of the fixed end mold respectively, the fixed end mold and two side molds together define a pouring position with an end opening, two openings of the pouring position are arranged facing each other; the track system includes a transverse track and a longitudinal track communicated with each other, two pouring positions are both positioned in the extension path of the transverse track, and the longitudinal track is positioned between two pouring positions.

Abstract: A memory unit with time domain edge delay accumulation for computing-in-memory applications is controlled by a first word line and a second word line. The memory unit includes at least one memory cell, at least one edge-delay cell multiplexor and at least one edge-delay cell. The at least one edge-delay cell includes a weight reader and a driver. The weight reader is configured to receive a weight and a multi-bit analog input voltage and generate a multi-bit voltage according to the weight and the multi-bit analog input voltage. The driver is connected to the weight reader and configured to receive an edge-input signal. The driver is configured to generate an edge-output signal having a delay time according to the edge-input signal and the multi-bit voltage. The delay time of the edge-output signal is positively correlated with the multi-bit analog input voltage multiplied by the weight.

Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.

Abstract: A magnetic multi-pole propulsion array system is applied to at least one external cathode and includes a plurality of magnetic multi-pole thrusters connected adjacent to each other. Each magnetic multi-pole thruster includes a propellant provider, a discharge chamber, an anode and a plurality of magnetic components. The propellant provider outputs propellant. The discharge chamber is connected with the propellant provider to accommodate the propellant. The anode is disposed inside the discharge chamber to generate an electric field. The plurality of magnetic components is respectively disposed on several sides of the discharge chamber. One of the several sides of the discharge chamber of the magnetic multi-pole thruster is applied for one side of a discharge chamber of another magnetic multi-pole thruster.

Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.

Abstract: A stator of a brushless motor is disclosed which includes a stator core, an insulating frame arranged on the stator core, and a plurality of windings wound around the insulating frame. The stator core includes a ring-shaped yoke part and a pole part mounted to the radial inner side of the yoke part. The pole part includes a plurality of teeth spaced-apart from each other along the circumferential direction, and a ring-shaped portion arranged at and connected to the radial inner side of the teeth. The radial outer sides of the teeth abut against the radial inner side of the yoke part. The insulating frame is arranged on the pole part. A plurality of power terminals are fixed to one axial end of the insulating frame and respectively electrically connected to the windings.

Abstract: Provided are methods of producing an acellular organ. The method includes the steps of, subjecting an organ derived from an animal to a static supercritical fluid (SCF) treatment followed by a dynamic SCF treatment. Optionally, the method of the present disclosure further includes a hypertonic and a hypotonic treatments prior to the static SCF treatment, and/or a neutralizing treatment after the dynamic SCF treatment. Also disclosed herein are acellular organs produced by the present method.

Abstract: The present invention relates to a judgment method for edge node computing result trustworthiness based on trust evaluation, and belongs to the technical field of data processing. By means of the present invention, a security mechanism for trustworthiness of a computing result output by an industrial edge node is guaranteed, the industrial edge node is prevented from outputting error data, and attacks of false data of malicious edge nodes are resisted, it is guaranteed that trustworthy computing results not be tampered are input in the industrial cloud, and a site device is made to receive correct computing results rather than malicious or meaningless messages, thereby improving efficiency and security of industrial production.

Abstract: A memory device includes a substrate, a first transistor and a second transistor, a first word line, a second word line, and a bit line. The first transistor and the second transistor are over the substrate and are electrically connected to each other, in which each of the first and second transistors includes first semiconductor layers and second semiconductor layers, a gate structure, and source/drain structures, in which the first semiconductor layers are in contact with the second semiconductor layers, and a width of the first semiconductor layers is narrower than a width of the second semiconductor layers. The first word line is electrically connected to the gate structure of the first transistor. The second word line is electrically connected to the gate structure of the second transistor. The bit line is electrically connected to a first one of the source/drain structures of the first transistor.

Abstract: The present disclosure provides a semiconductor structure and a method of manufacturing the same. The semiconductor structure includes a sensing device, a solar cell, and an interconnecting structure. The solar cell is disposed above the sensing device and is electrically connected to the sensing device. The interconnecting structure is disposed between the sensing device and the solar cell and has a first surface facing the solar cell and a second surface facing the sensing devices. The interconnecting structure comprises a first energy storage component and a second energy storage component. The first energy storage component is disposed closer to the first surface of the interconnecting structure than the second energy storage component.

Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.

Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.