Patents by Inventor Piyush Agarwal

Piyush Agarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9990992
    Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. A plurality of bitcells may be connectable to a common source voltage during a two-phase operation to place individual bitcells in intended impedance states.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: June 5, 2018
    Assignee: ARM Ltd.
    Inventors: Azeez Jennudin Bhavnagarwala, Lucian Shifren, Piyush Agarwal, Akshay Kumar, Robert Campbell Aitken
  • Publication number: 20180152197
    Abstract: Subject matter disclosed herein may relate to correlated electron switch devices, and may relate more particularly to digital to analog conversion using correlated electron switch devices ces.
    Type: Application
    Filed: December 29, 2017
    Publication date: May 31, 2018
    Inventors: Akshay Kumar, Piyush Agarwal, Bal S. Sandhu, Glen Arnold Rosendale
  • Patent number: 9972388
    Abstract: Disclosed are methods, systems and devices for powering up devices including non-volatile memory elements in an array of non-volatile memory elements. In one aspect, during a sequence for powering up an integrated device, non-volatile memory elements may be isolated from voltage supplies to avoid in advertent changes of memory states stored in the non-volatile memory elements.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: May 15, 2018
    Assignee: ARM Ltd.
    Inventors: Shidhartha Das, Piyush Agarwal, Akshay Kumar, Azeez Jennudin Bhavnagarwala
  • Publication number: 20180122463
    Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. Limiting current between terminals of the non-volatile memory device during read operations may enable use of higher voltages for higher realized gain.
    Type: Application
    Filed: September 21, 2017
    Publication date: May 3, 2018
    Inventors: Azeez Jennudin Bhavnagarwala, Piyush Agarwal, Akshay Kumar
  • Publication number: 20180114574
    Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. A plurality of bitcells may be connectable to a common source voltage during a two-phase operation to place individual bitcells in intended impedance states.
    Type: Application
    Filed: October 25, 2016
    Publication date: April 26, 2018
    Inventors: Azeez Jennudin Bhavnagarwala, Lucian Shifren, Piyush Agarwal, Akshay Kumar, Robert Campbell Aitken
  • Publication number: 20180114575
    Abstract: A method of writing a state to a correlated electron element in a storage circuit, comprising receiving a write command to write the state into the correlated electron element; reading a stored state of the correlated electron element; comparing the state and the stored state; and enabling a write driver to write the state into the correlated electron element when the state and read state are different.
    Type: Application
    Filed: December 14, 2017
    Publication date: April 26, 2018
    Applicant: ARM Limited
    Inventors: Shidhartha DAS, Andreas HANSSON, Akshay KUMAR, Piyush AGARWAL, Azeez Jennudin BHAVNAGARWALA, Lucian SHIFREN
  • Patent number: 9947402
    Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. Limiting current between terminals of the non-volatile memory device during read operations may enable use of higher voltages for higher realized gain. Additionally, bipolar write operations for set and reset may enable an increased write window and enhanced durability for a CES device.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: April 17, 2018
    Assignee: ARM Ltd.
    Inventors: Azeez Jennudin Bhavnagarwala, Vivek Asthana, Piyush Agarwal, Akshay Kumar, Lucian Shifren
  • Publication number: 20180102170
    Abstract: Disclosed are methods, systems and devices for powering up devices including non-volatile memory elements in an array of non-volatile memory elements. In one aspect, during a sequence for powering up an integrated device, non-volatile memory elements may be isolated from voltage supplies to avoid in advertent changes of memory states stored in the non-volatile memory elements.
    Type: Application
    Filed: October 12, 2016
    Publication date: April 12, 2018
    Inventors: Shidhartha Das, Piyush Agarwal, Akshay Kumar, Azeez Jennudin Bhavnagarwala
  • Patent number: 9882576
    Abstract: An analog-to-digital converter (ADC) and method of operation thereof are provided for converting an analog signal to a digital signal. The ADC utilizes Correlated Electron Material (CEM) devices that may contain a transition metal oxide (TMO), such as Nickel Oxide (NiO). The ADC may include an interconnect circuit that is operable to couple a power supply to the CEM devices. The power supply is controlled to program the resistance of the CEM devices and thereby control performance characteristics of the ADC.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: January 30, 2018
    Assignee: ARM Limited
    Inventors: Bal S. Sandhu, Piyush Agarwal, Akshay Kumar
  • Publication number: 20180019917
    Abstract: Example implementations relate to configuring a managed device. For example, configuration of a managed device may be performed by a services controller. The services controller may comprise a processing resource and a memory resource storing machine readable instructions to cause the processing resource to perform a number of actions. For instance, the services controller may manage configuration of a network using a hierarchical configuration model. The services controller may define a plurality of configuration elements for each of a plurality of managed devices in the hierarchical configuration model, where configuration elements shared among the plurality of managed devices are assigned a same setting from the services controller, and the configuration elements assigned by the services controller are customizable by each of the plurality of managed devices.
    Type: Application
    Filed: July 29, 2016
    Publication date: January 18, 2018
    Inventors: Piyush Agarwal, Raja Rangarajan, Chirag Vaidya, Joseph Baniqued, Senthil Kumar V.S., Toni Liu
  • Publication number: 20180019920
    Abstract: In some examples, the validation controller may comprise a processing resource and a memory resource storing machine readable instructions to cause the processing resource to perform a number of actions. In some examples, the validation controller may determine functional capabilities for a topology that includes a plurality of devices to be configured by the validation controller. The validation controller may compare a configuration element for the plurality of devices to the functional capabilities for the plurality of devices. The validation controller may validate the configuration element based on the comparison. The validation controller may also push the configuration element to the plurality of devices when the configuration element is validated.
    Type: Application
    Filed: January 31, 2017
    Publication date: January 18, 2018
    Inventors: Piyush Agarwal, Shreekanth Chandranna, Dhrumil Desai
  • Patent number: 9871528
    Abstract: Subject matter disclosed herein may relate to correlated electron switch devices, and may relate more particularly to digital to analog conversion using correlated electron switch devices ces.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: January 16, 2018
    Assignee: ARM Ltd.
    Inventors: Akshay Kumar, Piyush Agarwal, Bal S. Sandhu, Glen Arnold Rosendale
  • Patent number: 9859003
    Abstract: A method of writing a state to a correlated electron element in a storage circuit, comprising receiving a write command to write the state into the correlated electron element; reading a stored state of the correlated electron element; comparing the state and the stored state; and enabling a write driver to write the state into the correlated electron element when the state and read state are different.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: January 2, 2018
    Assignee: ARM Limited
    Inventors: Shidhartha Das, Andreas Hansson, Akshay Kumar, Piyush Agarwal, Azeez Jennudin Bhavnagarwala, Lucian Shifren
  • Publication number: 20170333449
    Abstract: The present invention relates to a method of treating allergic rhinitis in a subject (e.g., a human) in need thereof comprising nasally administering to the subject an effective amount of a fixed-dose pharmaceutical composition comprising mometasone or its salt and olopatadine or its salt.
    Type: Application
    Filed: June 28, 2017
    Publication date: November 23, 2017
    Inventors: Neelima KHAIRATKAR-JOSHI, Abhay Kulkami, Pradeep D. Wale, Vikram M. Bhosale, Piyush Agarwal, Patrick Keohane, Sudeesh K. Tantry, Chad Oh
  • Patent number: 9792984
    Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. Limiting current between terminals of the non-volatile memory device during read operations may enable use of higher voltages for higher realized gain.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: October 17, 2017
    Assignee: ARM Ltd.
    Inventors: Azeez Jennudin Bhavnagarwala, Piyush Agarwal, Akshay Kumar
  • Patent number: 9299124
    Abstract: Techniques described in the disclosure are generally related to reserving padding bytes in system memory when storing data in the system memory. The reserving of padding bytes may allow a memory interface to efficiently utilize the channels to the system memory when storing or subsequently retrieving the data.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: March 29, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Lin Chen, Piyush Agarwal, Long Chen, Lingjun Chen
  • Publication number: 20150312360
    Abstract: A computer detects an entry of content by a first user in a collaboration application and determines the entry of content contains an identification of a second user, the identification indicating the entry of content and the identification are to be visible only to the first user and the second user. Responsive to determining the entry of content contains the identification of a second user, the computer copies the entry of content. The computer then sends the copied entry of content to the second user in the collaboration application.
    Type: Application
    Filed: April 24, 2014
    Publication date: October 29, 2015
    Applicant: International Business Machines Corporation
    Inventors: Piyush Agarwal, James J. Antill, Vincent Burckhardt, Bernadette A. Carter
  • Publication number: 20150272966
    Abstract: The present invention relates to a method of treating allergic rhinitis in a subject (e.g., a human) in need thereof comprising nasally administering to the subject an effective amount of a fixed-dose pharmaceutical composition comprising mometasone or its salt and olopatadine or its salt.
    Type: Application
    Filed: April 8, 2015
    Publication date: October 1, 2015
    Inventors: Neelima KHAIRATKAR-JOSHI, Abhay KULKARNI, Dinesh Pradeep WALE, Vikram Mansingh BHOSALE, Piyush AGARWAL, Patrick KEOHANE, Sudeesh K. TANTRY, Chad OH
  • Patent number: 9091397
    Abstract: Apparatus and methods for sharing a gas panel among a plurality of multi-zone gas feed chambers of a plasma processing chamber. Each multi-zone gas feed chamber is provided with its own multi-zone gas feed device to adjustably split the incoming gas flow into each chamber and provide the different gas flows to different zones of the multi-zone gas feed chamber.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: July 28, 2015
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Iqbal Shareef, Piyush Agarwal, Evangelos Spyropoulos, Mark Taskar
  • Publication number: 20150155187
    Abstract: A system and method for processing a substrate in a processing chamber and providing an azimuthally evenly distributed draw on the processing byproducts using a gas pump down source coupled to the processing chamber above the plane of a substrate support within the processing chamber. The process chamber can include an annular plenum disposed between the support surface plane and the chamber top, the plenum including at least one vacuum inlet port coupled to the gas pump down source and a continuous inlet gap proximate to a perimeter of the substrate support, the continuous inlet gap having an inlet gas flow resistance of between about twice and about twenty times an outlet gas flow resistance the at least one vacuum inlet port.
    Type: Application
    Filed: December 4, 2013
    Publication date: June 4, 2015
    Applicant: LAM RESEARCH CORPORATION
    Inventors: Iqbal Shareef, Piyush Agarwal, Jason Augustino, Andreas Fischer