Abstract: A microelectronic assembly can include first and second microelectronic elements each embodying active semiconductor devices adjacent a front surface thereof, and having an electrically conductive pad exposed at the respective front surface. An interposer of material having a CTE less than 10 ppm/° C. has first and second surfaces attached to the front surfaces of the respective first and second microelectronic elements, the interposer having a second conductive element extending within an opening in the interposer. First and second conductive elements extend within openings extending from the rear surface of a respective microelectronic element of the first and second microelectronic elements towards the front surface of the respective microelectronic element.

Abstract: A microelectronic assembly is provided in which first and second electrically conductive pads exposed at front surfaces of first and second microelectronic elements, respectively, are juxtaposed, each of the microelectronic elements embodying active semiconductor devices. An electrically conductive element may extend within a first opening extending from a rear surface of the first microelectronic element towards the front surface thereof, within a second opening extending from the first opening towards the front surface of the first microelectronic element, and within a third opening extending through at least one of the first and second pads to contact the first and second pads. Interior surfaces of the first and second openings may extend in first and second directions relative to the front surface of the first microelectronic element, respectively, to define a substantial angle.

Abstract: An assembly and method of making same are provided. The assembly can be formed by juxtaposing a first electrically conductive element overlying a major surface of a first semiconductor element with an electrically conductive pad exposed at a front surface of a second semiconductor element. An opening can be formed extending through the conductive pad of the second semiconductor element and exposing a surface of the first conductive element. The opening may alternatively be formed extending through the first conductive element. A second electrically conductive element can be formed extending at least within the opening and electrically contacting the conductive pad and the first conductive element. A third semiconductor element can be positioned in a similar manner with respect to the second semiconductor element.

Abstract: An assembly and method of making same are provided. The assembly can be formed by stacking a first semiconductor element atop a second semiconductor element and forming an electrically conductive element extending through openings of the semiconductor elements. The openings may be staged. The conductive element can conform to contours of the interior surfaces of the openings and can electrically connect conductive pads of the semiconductor elements. A dielectric region can be provided at least substantially filling the openings of the semiconductor elements, and the electrically conductive element can extend through an opening formed in the dielectric region.

Abstract: A microelectronic unit includes a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality of active semiconductor devices adjacent the front surface, a plurality of conductive pads exposed at the front surface, and an opening extending through the semiconductor element. At least one of the conductive pads can at least partially overlie the opening and can be electrically connected with at least one of the active semiconductor devices. The microelectronic unit can also include a first conductive element exposed at the rear surface for connection with an external component, the first conductive element extending through the opening and electrically connected with the at least one conductive pad, and a second conductive element extending through the opening and insulated from the first conductive element. The at least one conductive pad can overlie a peripheral edge of the second conductive element.

Abstract: A method of fabricating a semiconductor assembly can include providing a semiconductor element having a front surface, a rear surface, and a plurality of conductive pads, forming at least one hole extending at least through a respective one of the conductive pads by processing applied to the respective conductive pad from above the front surface, forming an opening extending from the rear surface at least partially through a thickness of the semiconductor element, such that the at least one hole and the opening meet at a location between the front and rear surfaces, and forming at least one conductive element exposed at the rear surface for electrical connection to an external device, the at least one conductive element extending within the at least one hole and at least into the opening, the conductive element being electrically connected with the respective conductive pad.

Abstract: A method of forming a conductive element on a substrate and the resulting assembly are provided. The method includes forming a groove in a sacrificial layer overlying a dielectric region disposed on a substrate. The groove preferably extends along a sloped surface of the substrate. The sacrificial layer is preferably removed by a non-photolithographic method, such as ablating with a laser, mechanical milling, or sandblasting. A conductive element is formed in the groove. The grooves may be formed. The grooves and conductive elements may be formed along any surface of the substrate, including within trenches and vias formed therein, and may connect to conductive pads on the front and/or rear surface of the substrate. The conductive elements are preferably formed by plating and may or may not conform to the surface of the substrate.

Abstract: A method of fabricating a microelectronic unit includes providing a semiconductor element having a front surface and a rear surface remote from the front surface, forming at least one first opening extending from the rear surface partially through the semiconductor element towards the front surface by directing a jet of fine abrasive particles towards the semiconductor element, and forming at least one conductive contact and at least one conductive interconnect coupled thereto. The semiconductor element can include a plurality of active semiconductor devices therein. The semiconductor element can include a plurality of conductive pads exposed at the front surface. Each conductive interconnect can extend within one or more of the first openings and can be coupled directly or indirectly to at least one of the conductive pads. Each of the conductive contacts can be exposed at the rear surface of the semiconductor element for electrical connection to an external device.

Abstract: A microelectronic unit includes a microelectronic element, e.g., an integrated circuit chip, having a semiconductor region of monocrystalline form. The semiconductor region has a front surface extending in a first direction, an active circuit element adjacent the front surface, a rear surface remote from the front surface, and a conductive via which extends towards the rear surface. The conductive via can be insulated from the semiconductor region by an inorganic dielectric layer. An opening can extend from the rear surface partially through a thickness of the semiconductor region, with the opening and the conductive via having respective widths in the first direction. The width of the opening may be greater than the width of the conductive via where the opening meets the conductive via.

Abstract: A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity. The first chip may have vias extending from the cavity to the front surface and via conductors within these vias serving to connect the additional microelectronic element to the active elements of the first chip. The structure may have a volume comparable to that of the first chip alone and yet provide the functionality of a multi-chip assembly. A composite chip incorporating a body and a layer of semiconductor material mounted on a front surface of the body similarly may have a cavity extending into the body from the rear surface and may have an additional microelectronic element mounted in such cavity.

Abstract: A microelectronic unit, an interconnection substrate, and a method of fabricating a microelectronic unit are disclosed. A microelectronic unit can include a semiconductor element having a plurality of active semiconductor devices therein, the semiconductor element having a first opening extending from a rear surface partially through the semiconductor element towards a front surface and at least one second opening, and a dielectric region overlying a surface of the semiconductor element in the first opening. The microelectronic unit can include at least one conductive interconnect electrically connected to a respective conductive via and extending away therefrom within the aperture. In a particular embodiment, at least one conductive interconnect can extend within the first opening and at least one second opening, the conductive interconnect being electrically connected with a conductive pad having a top surface exposed at the front surface of the semiconductor element.

Abstract: A microelectronic unit includes a carrier structure having a front surface, a rear surface remote from the front surface, and a recess having an opening at the front surface and an inner surface located below the front surface of the carrier structure. The microelectronic unit can include a microelectronic element having a bottom surface adjacent the inner surface, a top surface remote from the bottom surface, and a plurality of contacts at the top surface. The microelectronic element can include terminals electrically connected with the contacts of the microelectronic element. The microelectronic unit can include a dielectric region contacting at least the top surface of the microelectronic element. The dielectric region can have a planar surface located coplanar with or above the front surface of the carrier structure. The terminals can be exposed at the surface of the dielectric region for interconnection with an external element.

Abstract: Structures for reducing the effect of charged surfaces near the electrodes on the performance efficiency of an electrohydrodynamic (EHD) device are disclosed. The potential levels on surfaces of an electronic device near the EHD electrodes are varied with respect to a function of the combination of distance from the emitter and the distance from the collector. The potential levels may be constant, may vary in discrete steps, may be continuously variable along the length between the EHD electrodes and beyond the electrodes, and may vary with respect to time.

Abstract: Embodiments of electrohydrodynamic (EHD) fluid accelerator devices utilize collector electrode structures that promote efficient fluid flow and reduce the probability of arcing by managing the strength of the electric field produced at the forward edges of the collector electrodes. In one application, the EHD devices dissipate heat generated by a thermal source in a thermal management system.

Abstract: In thermal management systems that employ EHD devices to motivate flow of air between ventilated boundary portions of an enclosure, it can be desirable to have some heat transfer surfaces participate in electrohydrodynamic acceleration of fluid flow while providing additional heat transfer surfaces that may not. In some embodiments, both collector electrodes and additional heat transfer surfaces are thermally coupled into a heat transfer path. Collector electrodes then contribute both to flow of cooling air and to heat transfer to the air flow so motivated. The collector electrodes and additional heat transfer surfaces may be parts of a unitary, or thermally coupled, structure that is introduced into a flow path at multiple positions therealong. In some embodiments, the collector electrodes and additional heat transfer surfaces may be proximate each other along the flow path. In some embodiments, the collector electrodes and additional heat transfer surfaces may be separate structures.

Abstract: Reversible flow may be provided in certain EHD device configurations that selectively energize corona discharge electrodes arranged to motivate flows in generally opposing directions. In some embodiments, a first set of one or more corona discharge electrodes is positioned, relative to a first array of collector electrode surfaces, to when energized, motivate flow in a first direction, while second set of one or more corona discharge electrodes is positioned, relative to a second array of collector electrode surfaces, to when energized, motivate flow in a second direction that opposes the first. In some embodiments, the first and second arrays of collector electrode surfaces are opposing surfaces of individual collector electrodes. In some embodiments, the first and second arrays of collector electrode surfaces are opposing surfaces of respective collector electrodes.

Abstract: In thermal management systems that employ EHD devices to motivate flow of air through an enclosure, spatial distribution of a ventilation boundary may facilitate reductions in flow resistance by reducing average transit distance for cooling air from an inlet portion of the ventilation boundary to an outlet portion. Some thermal management systems described herein distribute a ventilation boundary over opposing surfaces, adjacent surfaces or even a single surface of an enclosure while providing a short, “U” shaped, “L” shaped or generally straight through flow path. In some cases, spatial distributions of the ventilation boundary facilitate or enable enclosure geometries for which conventional fan or blower ventilation would be impractical.

Abstract: Performance of an electrohydrodynamic fluid accelerator device may be improved and adverse events such as sparking or arcing may be reduced based, amongst other things, on electrode geometries and/or positional interrelationships of the electrodes. For example, in a class of EHD devices that employ a longitudinally elongated corona discharge electrode (often, but not necessarily, a wire), a plurality of generally planar, collector electrodes may be positioned so as to present respective leading surfaces toward the corona discharge electrode. The generally planar collector electrodes may be oriented so that their major surfaces are generally orthogonal to the longitudinal extent of the corona discharge electrode. In such EHD devices, a high intensity electric field can be established in the “gap” between the corona discharge electrode and leading surfaces of the collector electrodes.