Abstract: An electronic door lock and a method for automatically judging a locking/unlocking direction of the electronic door lock are provided. The electronic door lock includes a latch assembly, a lock body, a transmission rod, a locking detection module, a motor module and a motion detection circuit board. The transmission rod is connected with the latch assembly for controlling the latch assembly. The motion detection circuit board is electrically connected with the motor module and the locking detection module. The motion detection circuit board controls the motor module to drive the transmission rod. Consequently, a latch bolt of the latch assembly is protruded out in a first direction or a second direction. By detecting the status of the transmission rod, the locking detection module judges whether the latch bolt is protruded to a locking position.

Abstract: The present invention provides a method for preventing and/or treating a NSAID-induced gastric ulcer. The method comprises administrating an effective amount of a lactic acid bacterium set to a subject. The lactic acid bacterium set comprises Lactobacillus plantarum GKD7 and Pediococcus acidilactici GKA4.

Abstract: Apparatuses, systems, and techniques to determine a configuration based at least in part on data stored by at least one data structure of a workload at runtime, and transform the workload into a sparse workload based at least in part on the configuration. In at least one embodiment, one or more sparse workloads (e.g., one or more sparse neural networks) are generated based at least in part on, for example, one or more workloads (e.g., one or more neural networks).

Abstract: A force sensing method, applied to a force sensing system comprising a plurality of force sensors and a touch sensing surface, comprising: (a) determining a first location of a first object on the touch sensing surface; (b) defining a first force sensing region according to the first location; and (c) computing a first system sensing force which the first object causes to the touch sensing surface according to the first location, and according to at least one sensor sensing force of a first part of the force sensors corresponding to the first force sensing region. The present invention also discloses a force sensing system which uses the above-mentioned force sensing method, and an efficient force sensor calibration method. Noises can be reduced and power consumption can be decreased, since only sensor sensing forces of force sensors near the object are used for computing the system sensing force.

Abstract: The present disclosure relates to a complex probiotic composition and a method for improving exercise performance of a subject with low intrinsic aerobic exercise capacity. The complex probiotic composition, which includes Lactobacillus rhamnosus GKLC1, Bifidobacterium lactis GKK24 and Clostridium butyricum GKB7, administered to the subject with the low intrinsic aerobic exercise capacity in a continuation period, can effectively reduce serum lactic acid and serum urea nitrogen after aerobic exercise, reduce proportion of offal fat and/or increase liver and muscle glycogen contents, thereby being as an effective ingredient for preparation of various compositions.

Abstract: An out-of-order buffer includes an out-of-order queue and a controlling circuit. The out-of-order queue includes a request sequence table and a request storage device. The controlling circuit receives and temporarily stores the plural requests into the out-of-order queue. After the plural requests are transmitted to plural corresponding target devices, the controlling circuit retires the plural requests. The request sequence table contains m×n indicating units. The request sequence table contains m entry indicating rows. Each of the m entry indicating rows contains n indicating units. The request storage device includes m storage units corresponding to the m entry indicating rows in the request sequence table. The state of indicating whether one request is stored in the corresponding storage unit of the m storage units is recoded in the request sequence table. The storage sequence of the plural requests is recoded in the request sequence table.

Abstract: A high electron mobility transistor device including a channel layer, a first barrier layer, and a P-type gallium nitride layer is provided. The first barrier layer is disposed on the channel layer. The P-type gallium nitride layer is disposed on the first barrier layer. The first thickness of the first barrier layer located directly under the P-type gallium nitride layer is greater than the second thickness of the first barrier layer located on two sides of the P-type gallium nitride layer.

Abstract: A base is configured for a bracket. The base includes a hollow body, a plurality of supporting branches, and an illuminating module. The hollow body is connected to the bracket and has a bottom part and a first sidewall. The bottom part has an open hole. The first sidewall has a transparent structure. The plurality of supporting branches is disposed around the hollow body to lift the hollow body. The illuminating module is disposed in the hollow body and includes a sleeve and a base plate. The sleeve has a second sidewall, a first end, and a second end opposite to the first end. The second sidewall has an opening. The position of the opening is corresponding to the transparent structure. The base plate is disposed on the first end. The base plate is provided with a light source. The light source projects light beams toward the second end.

Abstract: A trench-gate field effect transistor includes a plurality of trenches, a plurality of gate electrode units, and a plurality of source electrode units. Each of the trenches has a first trench region, a second trench region having a width less than that of the first trench region, and a neck trench region extending between the first trench region and the second trench region. Each of the gate electrode units includes a pair of first gate electrode portions disposed in the first trench region, a pair of second gate electrode portions disposed in the neck trench region, and a third gate electrode portion disposed in the second trench region. Each of the source electrode units includes a first source electrode portion disposed between a pair of the first gate electrode portions, and a second source electrode portion connected to the first source electrode portion.

Abstract: A container with a handle includes a container body. The container body has a peripheral edge extending outward to form a ring portion. The ring portion is provided with a first slot penetrating through the ring portion. The first slot cuts the ring portion to form a first handle portion and a first edge portion completely connected to the container body. In addition, the ring portion is further provided with a second slot penetrating through the ring portion. The first slot and the second slot are respectively located on two opposite sides of the ring portion. The second slot cuts the ring portion to form a second handle portion and a second edge portion completely connected to the container body. The first handle portion and the second handle portion each have two ends connected to the container body and may be pulled up as the handle.

Abstract: Hierarchical structured sparse parameter pruning and processing improves runtime performance and energy efficiency of neural networks. In contrast with conventional (non-structured) pruning which allows for any distribution of the non-zero values within a matrix that achieves the desired sparsity degree (e.g., 50%) and is consequently difficult to accelerate, structured hierarchical sparsity requires each multi-element unit at the coarsest granularity of the hierarchy to be pruned to the desired sparsity degree. The global desired sparsity degree is a function of the per-level sparsity degrees. Distribution of non-zero values within each multi-element unit is constrained according to the per-level sparsity degree at the particular level of the hierarchy. Each level of the hierarchy may be associated with a hardware (e.g., logic or circuit) structure that can be enabled or disabled according to the per-level sparsity.

Abstract: Accelerators are generally utilized to provide high performance and energy efficiency for tensor algorithms. Currently, an accelerator will be specifically designed around the fundamental properties of the tensor algorithm and shape it supports, and thus will exhibit sub-optimal performance when used for other tensor algorithms and shapes. The present disclosure provides a flexible accelerator for tensor workloads. The flexible accelerator can be a flexible tensor accelerator or a FPGA having a dynamically configurable inter-PE network supporting different tensor shapes and different tensor algorithms including at least a GEMM algorithm, a 2D CNN algorithm, and a 3D CNN algorithm, and/or having a flexible DPU in which a dot product length of its dot product sub-units is configurable based on a target compute throughput.

Abstract: Accelerators are generally utilized to provide high performance and energy efficiency for tensor algorithms. Currently, an accelerator will be specifically designed around the fundamental properties of the tensor algorithm and shape it supports, and thus will exhibit sub-optimal performance when used for other tensor algorithms and shapes. The present disclosure provides a flexible accelerator for tensor workloads. The flexible accelerator can be a flexible tensor accelerator or a FPGA having a dynamically configurable inter-PE network supporting different tensor shapes and different tensor algorithms including at least a GEMM algorithm, a 2D CNN algorithm, and a 3D CNN algorithm, and/or having a flexible DPU in which a dot product length of its dot product sub-units is configurable based on a target compute throughput that is less than or equal to a maximum throughput of the flexible DPU.

Abstract: Examples provide two-tiered scheduling within a cluster. A coarse-grained analysis is performed on a candidate set of hosts to select a host for a virtual computing instance based on optimization of at least one resource. A host is selected based on the analysis results. The identified virtual computing instance is placed on the selected host. A fine-grained analysis is performed on a set of communication graphs for a plurality of virtual computing instances to generate a set of penalty scores. A set of communicating virtual computing instances are selected based on the set of penalty scores. A first virtual computing instance from a first host is relocated to a second host to minimize a distance between the first virtual computing instance and a second virtual computing instance. Relocating the first virtual computing instance reduces at least one penalty score for the set of communicating virtual computing instances.

Abstract: A fabricating method of a shielded gate MOSFET is provided, includes the steps of forming a semiconductor substrate having a trench, forming a sacrifice oxide layer in the trench, the sacrifice oxide layer covering a side wall of the trench, forming a source polycrystalline silicon region in the trench, forming an insulation oxide layer above the source polycrystalline silicon region to have the source polycrystalline silicon region fully enclosed by the sacrifice oxide layer and the insulation oxide layer, depositing polycrystalline silicon into the trench and carrying out a back etching to control a thickness of the insulation oxide layer above the source polycrystalline silicon region, forming a gate oxide layer in the trench, the gate oxide layer covering the side wall of the trench, forming a gate polycrystalline silicon region in the trench, and forming a body layer and a heavily doped region around the trench in an ion implantation manner.

Abstract: A fabricating method of a shielded gate MOSFET is provided, including steps of: forming a semiconductor substrate having a trench; forming a sacrifice oxide layer in the trench, the sacrifice oxide layer covering a side wall of the trench; forming a source polycrystalline silicon region in the trench; forming an insulation oxide layer above the source polycrystalline silicon region to have the source polycrystalline silicon region fully enclosed by the sacrifice oxide layer and the insulation oxide layer; depositing polycrystalline silicon into the trench and carrying out a back etching to control a thickness of the insulation oxide layer above the source polycrystalline silicon region; forming a gate oxide layer in the trench, the gate oxide layer covering the side wall of the trench; forming a gate polycrystalline silicon region in the trench; and forming a body layer and a heavily doped region around the trench in an ion implantation manner.

Abstract: A projecting device is provided. The projecting device is adapted to assembling with an electronic device. The projecting device comprises a main body, a light emitting portion, a rotating portion, and an adjusting portion. The main body includes a first opening and a second opening. The light emitting portion is disposed in the main body, and transmits a light through the first opening. The rotating portion is disposed in the main body and connected with the light emitting portion. The adjusting portion is disposed in the second opening and connected with the rotating portion. The light emitting portion drives the rotating portion to rotate through the adjusting portion to adjust the angle of the light.

Abstract: Examples provide two-tiered scheduling within a cluster. A coarse-grained analysis is performed on a candidate set of hosts to select a host for a virtual computing instance based on optimization of at least one resource. A host is selected based on the analysis results. The identified virtual computing instance is placed on the selected host. A fine-grained analysis is performed on a set of communication graphs for a plurality of virtual computing instances to generate a set of penalty scores. A set of communicating virtual computing instances are selected based on the set of penalty scores. A first virtual computing instance from a first host is relocated to a second host to minimize a distance between the first virtual computing instance and a second virtual computing instance. Relocating the first virtual computing instance reduces at least one penalty score for the set of communicating virtual computing instances.

Abstract: Examples provide two-tiered scheduling within a cluster. A coarse-grained analysis is performed on a candidate set of hosts to select a host for a virtual computing instance based on optimization of at least one resource. A host is selected based on the analysis results. The identified virtual computing instance is placed on the selected host. A fine-grained analysis is performed on a set of communication graphs for a plurality of virtual computing instances to generate a set of penalty scores. A set of communicating virtual computing instances are selected based on the set of penalty scores. A first virtual computing instance from a first host is relocated to a second host to minimize a distance between the first virtual computing instance and a second virtual computing instance. Relocating the first virtual computing instance reduces at least one penalty score for the set of communicating virtual computing instances.

Abstract: A projecting device is provided. The projecting device is adapted to assembling with an electronic device. The projecting device comprises a main body, a light emitting portion, a rotating portion, and an adjusting portion. The main body includes a first opening and a second opening. The light emitting portion is disposed in the main body, and transmits a light through the first opening. The rotating portion is disposed in the main body and connected with the light emitting portion. The adjusting portion is disposed in the second opening and connected with the rotating portion. The light emitting portion drives the rotating portion to rotate through the adjusting portion to adjust the angle of the light.