Patents by Inventor Po Chien
Po Chien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12009238Abstract: The present disclosure provides a method for fabricating a semiconductor structure, including disposing a mask at a first position in a first chamber, generating; a first plurality of ions toward the mask by an ionizer, forming a photoresist layer on a substrate, receiving the substrate in the first chamber, and exposing the photoresist layer with actinic radiation through the mask in the first chamber.Type: GrantFiled: June 30, 2021Date of Patent: June 11, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Po-Chien Huang, Chung-Hung Lin, Chih-Wei Wen
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Patent number: 11987431Abstract: A top-opening substrate carrier comprises a container body, a door member and at least one latching mechanism. The latching mechanism includes a rotary drive member, a first driven cam, a second driven cam, a first connecting rod, a second connecting rod, two longitudinal latching arms and two lateral latching arms. The first driven cam and the second driven cam are disposed at two sides of the rotary drive member. When the rotary drive member is rotated by force, it links and activates the first connecting rod and the second connecting rod to synchronously drive the first driven cam and the second driven cam to rotate, thereby driving the two longitudinal latching arms and the two lateral latching arms to project towards locking holes of the container body and locked, or retract from the locking holes of the container body and unlocked.Type: GrantFiled: March 27, 2023Date of Patent: May 21, 2024Assignee: GUDENG PRECISION INDUSTRIAL CO., LTD.Inventors: Ming-Chien Chiu, Yung-Chin Pan, Cheng-En Chung, Chih-Ming Lin, Po-Ting Lee, Wei-Chien Liu, Tzu-Ning Huang
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Patent number: 11978496Abstract: A method includes generating a differential voltage from a first reference voltage generator; receiving the differential voltage at a second reference voltage generator; dividing the differential voltage at the second reference voltage generator into multiple available reference voltage levels; and selecting one of the available reference voltage levels to apply to a circuit.Type: GrantFiled: April 27, 2022Date of Patent: May 7, 2024Assignee: NVIDIA CORP.Inventors: Jiwang Lee, Jaewon Lee, Po-Chien Chiang, Hsuche Nee, Wen-Hung Lo, Michael Ivan Halfen, Abhishek Dhir
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Publication number: 20240140553Abstract: A foldable electric bicycle includes a foldable body, a first sensing object, a motor, a motor controller, and a first sensor. The foldable body includes a first frame, a second frame, and a latch. The first frame is foldably connected to the second frame to make the first frame operably unfolded to a safe state or folded to a folded state relative to the second frame. The first sensing object is disposed on the latch. The latch is disposed on the second frame. The first sensor is disposed on the first frame. When the first sensor cannot sense the first sensing object, the motor controller turns off the motor.Type: ApplicationFiled: November 1, 2023Publication date: May 2, 2024Applicant: DARAD INNOVATION CORPORATIONInventors: Po-Jen Hsu, Lun-Chien Kou
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Publication number: 20240144098Abstract: Aspects of the present disclosure provide an automated labeling system. For example, the automated labeling system can include an automated labeling module (ALM) configured to receive wireless signals and ground truth of learning object and label the wireless signals with the ground truth when receiving the ground truth to generate labeled training data. The automated labeling system can also include a training database coupled to the ALM. The training database can be configured to store the labeled training data.Type: ApplicationFiled: October 16, 2023Publication date: May 2, 2024Applicant: MEDIATEK INC.Inventors: Chao Peng WANG, Chia-Da LEE, Po-Yu CHEN, Hsiao-Chien CHIU, Yi-Cheng LU
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Patent number: 11973501Abstract: A multi-rank circuit system includes multiple transmitters each switchably coupled to a first end of a shared input/output (IO) channel and a unified receiver coupled to a second end of the shared IO channel. The unified receiver is coupled to apply a preconfigured analog reference voltage to set a differential output of the unified receiver, and further configured to apply a variable digital code to adjust the differential output according to a particular one of the transmitters that is switched to the shared IO channel.Type: GrantFiled: April 27, 2022Date of Patent: April 30, 2024Assignee: NVIDIA CORP.Inventors: Jiwang Lee, Jaewon Lee, Hsuche Nee, Po-Chien Chiang, Wen-Hung Lo, Michael Ivan Halfen, Abhishek Dhir
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Patent number: 11955794Abstract: A surge protection system includes a receptacle body, at least one power output jack, a power obtaining device, at least one surge protection module, a microcontroller unit, and a surge detection circuit. The at least one surge protection module includes a housing, a memory element, and a surge protection circuit that includes a surge absorption element and a thermal fuse connected in series and parallel. The surge absorption element absorbs a surge inputted from an external power supply, and the memory element records a number of surges carried by the surge absorption element. When the surge enters the surge protection system from the external power supply, the surge absorption element absorbs the surge, and the surge detection circuit outputs a signal to the microcontroller unit that writes the number of surges carried by the surge absorption element into the memory element.Type: GrantFiled: May 25, 2022Date of Patent: April 9, 2024Assignee: POWERTECH INDUSTRIAL CO., LTD.Inventors: Jung-Hui Hsu, Po-Hua Hsu, Chi-Chien Chen
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Patent number: 11948820Abstract: The present invention provides a latching guide structure arranged inside a door of semiconductor carrier. The latching guide structure comprises an upper latching part, a lower latching part, at least one elastic unit and a driver. Moreover, a first guiding portion of the upper latching part is matched with a second guiding portion of the lower latching part, therefore to define the installation space for the at least one elastic unit. On the other hand, the driver simultaneously actuates an upper actuating unit of the first guiding portion and a lower actuating unit of the second guiding portion to linearly move in reverse direction therebetween. The range of the linear motion of the upper actuating unit and the lower actuating unit represents the compression or extension of the at least one elastic unit, determining to control the open/close status of the upper latching part and the lower latching part.Type: GrantFiled: November 28, 2022Date of Patent: April 2, 2024Assignee: GUDENG PRECISION INDUSTRIAL CO., LTD.Inventors: Ming-Chien Chiu, Chih-Ming Lin, Cheng-Han Chou, Po-Ting Lee
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Publication number: 20240105481Abstract: The present invention provides a latching guide structure arranged inside a door of semiconductor carrier. The latching guide structure comprises an upper latching part, a lower latching part, at least one elastic unit and a driver. Moreover, a first guiding portion of the upper latching part is matched with a second guiding portion of the lower latching part, therefore to define the installation space for the at least one elastic unit. On the other hand, the driver simultaneously actuates an upper actuating unit of the first guiding portion and a lower actuating unit of the second guiding portion to linearly move in reverse direction therebetween. The range of the linear motion of the upper actuating unit and the lower actuating unit represents the compression or extension of the at least one elastic unit, determining to control the open/close status of the upper latching part and the lower latching part.Type: ApplicationFiled: November 28, 2022Publication date: March 28, 2024Inventors: MING-CHIEN CHIU, CHIH-MING LIN, CHENG-HAN CHOU, PO-TING LEE
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Patent number: 11916314Abstract: A mobile device includes a housing, a first radiation element, a second radiation element, a third radiation element, a first switch element, and a second switch element. The first radiation element has a first feeding point. The second radiation element has a second feeding point. The first radiation element, the second radiation element, and the third radiation element are distributed over the housing. The first switch element is closed or open, so as to selectively couple the first radiation element to the third radiation element. The second switch element is closed or open, so as to selectively couple the second radiation element to the third radiation element. An antenna structure is formed by the first radiation element, the second radiation element, and the third radiation element.Type: GrantFiled: May 12, 2022Date of Patent: February 27, 2024Assignee: HTC CorporationInventors: Cheng-Hung Lin, Szu-Po Wang, Chia-Te Chien, Chun-Chieh Wang, Kang-Ling Li, Chun-Hsien Lee, Yu-Chieh Chiu
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Patent number: 11881255Abstract: A multi-rank circuit system utilizing a shared IO channel includes a first stage of multiple selectors coupled to input multiple digital busses, and a second stage including one or more selectors coupled to receive outputs of the first stage of selectors and to individually select one of the outputs of the first stage of selectors to one or more control circuits for IO circuits of the ranks. The system switches one of the ranks to be an active rank on the shared IO channel, and operates the first stage of selectors to select one of the digital busses to the second stage of selectors in advance of switching a next active rank to the shared IO channel.Type: GrantFiled: April 27, 2022Date of Patent: January 23, 2024Assignee: NVIDIA CORP.Inventors: Jiwang Lee, Jaewon Lee, Hsuche Nee, Po-Chien Chiang, Wen-Hung Lo, Abhishek Dhir, Michael Ivan Halfen, Chunjen Su
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Publication number: 20230352077Abstract: A method includes generating a differential voltage from a first reference voltage generator; receiving the differential voltage at a second reference voltage generator; dividing the differential voltage at the second reference voltage generator into multiple available reference voltage levels; and selecting one of the available reference voltage levels to apply to a circuit.Type: ApplicationFiled: April 27, 2022Publication date: November 2, 2023Applicant: NVIDIA Corp.Inventors: Jiwang Lee, Jaewon Lee, Po-Chien Chiang, Hsuche Nee, Wen-Hung Lo, Michael Ivan Halfen, Abhishek Dhir
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Publication number: 20230352081Abstract: A multi-rank circuit system utilizing a shared IO channel includes a first stage of multiple selectors coupled to input multiple digital busses, and a second stage including one or more selectors coupled to receive outputs of the first stage of selectors and to individually select one of the outputs of the first stage of selectors to one or more control circuits for IO circuits of the ranks. The system switches one of the ranks to be an active rank on the shared IO channel, and operates the first stage of selectors to select one of the digital busses to the second stage of selectors in advance of switching a next active rank to the shared IO channel.Type: ApplicationFiled: April 27, 2022Publication date: November 2, 2023Applicant: NVIDIA Corp.Inventors: Jiwang Lee, Jaewon Lee, Hsuche Nee, Po-Chien Chiang, Wen-Hung Lo, Abhishek Dhir, Michael Ivan Halfen, CHUNJEN SU
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Publication number: 20230352078Abstract: The differential voltage output from a first reference voltage generator of a multi-rank circuit is trained on multiple ranks of the multi-rank circuit. Multiple local reference voltage generators are trained to generate reference voltages for communication on the individual ranks, where the reference voltages output by the local reference voltage generators fall within a range of the differential voltage output.Type: ApplicationFiled: April 27, 2022Publication date: November 2, 2023Applicant: NVIDIA Corp.Inventors: Jiwang Lee, Jaewon Lee, Wen-Hung Lo, Michael Ivan Halfen, Abhishek Dhir, Hsuche Nee, Po-Chien Chiang
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Publication number: 20230353155Abstract: A multi-rank circuit system includes multiple transmitters each switchably coupled to a first end of a shared input/output (IO) channel and a unified receiver coupled to a second end of the shared IO channel. The unified receiver is coupled to apply a preconfigured analog reference voltage to set a differential output of the unified receiver, and further configured to apply a variable digital code to adjust the differential output according to a particular one of the transmitters that is switched to the shared IO channel.Type: ApplicationFiled: April 27, 2022Publication date: November 2, 2023Applicant: NVIDIA Corp.Inventors: Jiwang Lee, Jaewon Lee, Hsuche Nee, Po-Chien Chiang, Wen-Hung Lo, Michael Ivan Halfen, Abhishek Dhir
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Patent number: 11603161Abstract: The disclosure provides a bicycle caliper including a casing assembly and a plurality of pistons. The casing assembly has a first fluid inlet, a second fluid inlet, a first fluid channel, a plurality of piston chambers, and a second fluid channel. The first fluid channel has a first connection opening and a second connection opening opposite to each other. The first connection opening and the second connection opening of the first fluid channel are respectively in fluid communication with the first fluid inlet and the second fluid inlet. The first fluid channel penetrates through the piston chambers. Two opposite openings of the second fluid channel are respectively in fluid communication with the first connection opening and the second connection opening of the first fluid channel, and the second fluid channel does not penetrate through the piston chambers. The pistons are respectively and movably disposed in the piston chambers.Type: GrantFiled: November 5, 2020Date of Patent: March 14, 2023Assignee: TEKTRO TECHNOLOGY CORPORATIONInventors: Chao-Kung Chen, Po-Chien Tsai
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Patent number: 11488771Abstract: An adapter is provided and having a circuit board, primary components and secondary components installed on the circuit board, a shielding plate disposed between the primary components and the secondary components, and a transformer installed on the circuit board. The transformer has a bobbin, an iron core set assembled with the bobbin, at least one movable pin, at least one first winding, and at least one second winding. The movable pin is able to be positioned at an upper position for allowing the iron core set to be assembled with the bobbin or for allowing the first winding and the second winding to be wound onto the winding portion, and the movable pin is able to be positioned at a lower position when the transformer is installed onto the circuit board. Thereby, the adapter can be assembled in an automated process with improved assembly efficiency and high production yields.Type: GrantFiled: January 22, 2020Date of Patent: November 1, 2022Assignee: CHICONY POWER TECHNOLOGY CO., LTD.Inventors: Po-Chien Chou, Che-Shih Lin
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Publication number: 20220285226Abstract: One or more embodiments of the present disclosure describe an artificial intelligence assisted substrate defect repair apparatus and method. The AI assisted defect repair apparatus employs an object detection algorithm. Based on the plurality of images taken by detectors located at different respective positions, the detectors capture various views of an object including a defect. The composition information as well as the morphology information (e.g., shape, size, location, height, depth, width, length, or the like) of the defect and the object are obtained based on the plurality of images. The object detection algorithm analyzes the images and determines the type of defect and the recommends a material (e.g., etching gas) and the associated information (e.g., supply time of the etching gas, flow rate of the etching gas, etc.) for fixing the defect.Type: ApplicationFiled: July 29, 2021Publication date: September 8, 2022Inventors: Po-Chien HUANG, Chung-Hung LIN, Chih-Wei WEN
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Publication number: 20220199306Abstract: A transformer includes a bobbin. The bobbin includes a main body, a connection member, and a terminal base. The main body is wound by a coil. Two sides of the connection member are respectively connected to the main body and the terminal base. A plurality of connection terminals of the coil extend to the terminal base through a wire trough of the main body and are connected to pins of the terminal base. The connection member is cut off by automated machining, and the terminal base is mounted on a surface of a housing of the transformer, and no pin is disposed on the housing. Hence, the overall size of the transformer is effectively reduced.Type: ApplicationFiled: March 29, 2021Publication date: June 23, 2022Inventors: Po-Chien Chou, Che-Shih Lin, Yi-Wei Su
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Patent number: 11205496Abstract: A programmable testing apparatus imposes power interruptions on a storage device at any given point of time under at least one workload according to at least one protocol for tests. The programmable testing apparatus includes a controller unit connected to a workload unit, a power control unit, a protocol control unit and a data buffer unit. The controller unit calculates and receives and replies commands in the tests. The workload unit imposes various workloads on the storage device. The power control unit imposes power interruptions on the storage device under control of the controller unit. The protocol control unit provides commands according to the protocol for tests. The data buffer unit stores critical data and information to check whether data stored in the storage device are correct.Type: GrantFiled: September 4, 2020Date of Patent: December 21, 2021Assignees: GOKE TAIWAN RESEARCH LABORATORY LTD., XINSHENG INTELLIGENT TECHNOLOGY CO., LTD.Inventors: Po-Chien Chang, Ru-Yi Yang, Po-Wen Hsieh