Patents by Inventor Po-Chih HUANG

Po-Chih HUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11995826
    Abstract: An auxiliary screening system and an auxiliary screening method for a hip joint of a baby are provided. The auxiliary screening method includes: collecting plural images of the hip joint; performing an image analysis operation on each of the images of the hip joint to extract plural image features of each of the images of the hip joint and determining whether each of the images of the hip joint is a standard image according to the image features of each of the images of the hip joint; and when at least one of the images of the hip joint is determined as the standard image, plural angle parameters are calculated and the at least one of the images of the hip joint that is determined as the standard image is outputted, in which the angle parameters include values of an angle ? and an angle ?.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: May 28, 2024
    Assignee: METAL INDUSTRIES RESEARCH & DEVELOPMENT CENTRE
    Inventors: Po-Chih Shen, Bing-Feng Huang, Jin-Yuan Syue, Hsiang-Hsiang Chou
  • Publication number: 20240147661
    Abstract: A zoned heat dissipation control system for a water cooling radiator and a water cooling heat dissipation system having the zoned heat dissipation control system includes a plurality of fans, a plurality of heat dissipation zones defined on the water cooling radiator, a thermal detector, and a control unit. At least one of the fans is disposed within each of the heat dissipation zones. The thermal detector is disposed within at least one of the heat dissipation zones and configured to detect the temperature of the water cooling radiator. The control unit is electrically connected to the fans and the thermal detector and configured to modulate the rotational speed of the fan within each of the heat dissipation zones based on the detected data from the thermal detector.
    Type: Application
    Filed: October 31, 2023
    Publication date: May 2, 2024
    Inventors: SHUN-CHIH HUANG, TAI-CHUAN MAO, PO-SHENG CHIU, WEI-EN SHIH, CHIH-CHIA LIN
  • Publication number: 20240125849
    Abstract: An RF testing method is applied between a testing instrument and multiple devices under test at least including a first DUT and a second DUT. The testing instrument includes a signal generator and a signal analyzer. A sync signal is sent to the testing instrument and the first DUT, so that the first DUT occupies the signal generator to receive a testing signal from the signal generator. The first DUT sends an uplink signal to the signal analyzer based on the testing signal to occupy the signal analyzer for signal analysis at a first point in time. The sync signal is sent to the testing instrument and the second DUT, so that the second DUT occupies the signal generator to receive the testing signal from the signal generator at a second point in time. The first point in time is parallel to the second point in time.
    Type: Application
    Filed: March 8, 2023
    Publication date: April 18, 2024
    Inventors: Jung-Yin CHIEN, Po-Yen TSENG, Pin-Lin HUANG, Wen-Chih CHEN
  • Patent number: 11942906
    Abstract: The present invention provides a transmitter including a mixer, a harmonic impedance adjustment circuit and an amplifier. The mixer is configured to mix a first baseband signal with a first oscillation signal to generate a first mixed signal to a first node, and to mix a second baseband signal with a second oscillation signal to generate a second mixed signal to a second node. The harmonic impedance adjustment circuit is coupled between the first node and the second node, and is configured to reduce harmonic components of the first mixed signal and the second mixed signal to generate an adjusted first mixed signal and an adjusted second mixed signal. The amplifier is coupled to the harmonic impedance adjustment circuit, and is configured to generate an amplified signal according to the adjusted first mixed signal and the adjusted second mixed signal.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: March 26, 2024
    Assignee: Realtek Semiconductor Corp.
    Inventors: Ting-Yao Huang, Teng-Yuan Chang, Po-Chih Wang, Ka-Un Chan
  • Publication number: 20230197421
    Abstract: A method includes loading a wafer over a wafer chuck in a process chamber; performing a deposition process on the loaded wafer; supplying a fluid medium to a fluid guiding structure in the wafer chuck from a fluid inlet port on the wafer chuck, the fluid guiding structure comprising a plurality of arc-shaped channels fluidly communicated with each other; guiding the fluid medium from a first one of the arc-shaped channels of the fluid guiding structure to a second one of the arc-shaped channels of the fluid guiding structure. The second one of the arc-shaped channels of the fluid guiding structure is concentric with the first one of the arc-shaped channels of the fluid guiding structure from a top view.
    Type: Application
    Filed: February 22, 2023
    Publication date: June 22, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Chun YANG, Yi-Ming LIN, Po-Wei LIANG, Chu-Han HSIEH, Chih-Lung CHENG, Po-Chih HUANG
  • Publication number: 20230103322
    Abstract: An end cap for a carriage of a linear guide. The end cap has a closed lubrication port which is openable by operatively connecting a lubrication fitting to the lubrication port. The is formed by injection molding and the closed lubrication port of the end cap is formed by rotary demolding.
    Type: Application
    Filed: October 4, 2022
    Publication date: April 6, 2023
    Inventors: Andreas Drügemöller, Yung-Chang Chiou, Po-Chih Huang, Fung Cheung
  • Publication number: 20230067115
    Abstract: A system and method for generating a gas curtain over an access port of a processing chamber for a semiconductor substrate. A gas flow stabilizer and a gas flow receiver, each including a horizontal flow section and a vertical flow section cooperate to generate a gas curtain that impedes gas, e.g., oxygen, from outside the processing chamber, from flowing into the chamber, for example, when the access port is opened to add/or to remove a workpiece from the processing chamber.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: Sheng-chun YANG, Po-Chih HUANG, Chih-Lung CHENG, Yi-Ming LIN, Chen-Hao LIAO, Min-Cheng CHUNG
  • Publication number: 20230069237
    Abstract: The present disclosure provides a method and a system therefore for processing wafer. The method includes: extracting a first gas from a chamber via a first route; blocking a second route used to be pumped down to chuck a wafer placed in the chamber, wherein the second route connects the chamber and the first route; and providing a second gas via a third route to purge a junction of the first route and the second route.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: SHENG-CHUN YANG, CHIH-LUNG CHENG, YI-MING LIN, PO-CHIH HUANG, YU-HSIANG JUAN, XUAN-YANG ZHENG, REN-JYUE WANG, CHIH-YUAN WANG
  • Patent number: 11594401
    Abstract: A method for processing semiconductor wafer is provided. The method includes loading a semiconductor wafer on a top surface of a wafer chuck. The method also includes supplying a gaseous material between the semiconductor wafer and the top surface of the wafer chuck through a first gas inlet port and a second gas inlet port located underneath a fan-shaped sector of the top surface. The method further includes supplying a fluid medium to a fluid inlet port of the wafer chuck and guiding the fluid medium from the fluid inlet port to flow through a number of arc-shaped channels located underneath the fan-shaped sector of the top surface. In addition, the method includes supplying a plasma gas over the semiconductor wafer.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Chun Yang, Yi-Ming Lin, Po-Wei Liang, Chu-Han Hsieh, Chih-Lung Cheng, Po-Chih Huang
  • Publication number: 20220403945
    Abstract: A valve for throttling gas flow from a semiconductor processing tool includes a valve body. A shaft extends through the valve body. The shaft defines an internal cavity and a first opening communicating with the internal cavity. A first deflector is positioned on the shaft proximate the first opening and directed at a first interface between the shaft and the valve body. A method for throttling gas flow from a semiconductor processing tool includes providing a gas in an internal cavity defined in a shaft of a valve and directing the gas through an opening defined in the shaft and communicating with the bore toward an interface between the shaft and a valve body of the valve supporting the shaft.
    Type: Application
    Filed: April 8, 2022
    Publication date: December 22, 2022
    Inventors: Sheng-Chun Yang, Po-Chih Huang, Chang Chun, Xuan-Yang Zheng, Tzu-Chuan Chao, Ren-Jyue Wang
  • Publication number: 20220384239
    Abstract: A wafer fabricating system includes a wafer chuck, a gas inlet port, a fluid inlet port, first and second arc-shaped channels, a gas source, and a fluid containing source. The wafer chuck has a top surface, and orifices are formed on the top surface. The gas inlet port is formed in the wafer chuck and located underneath a fan-shaped sector of the top surface, wherein the gas inlet port is fluidly communicated with the orifices. The fluid inlet port is formed in the wafer chuck. The first and second arc-shaped channels are fluidly communicated with the fluid inlet port and located underneath the fan-shaped sector of the top surface and located at opposite sides of the gas inlet port from a top view. The gas source fluidly is connected to the gas inlet port. The fluid containing source fluidly is connected to the fluid inlet port.
    Type: Application
    Filed: August 8, 2022
    Publication date: December 1, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Chun YANG, Yi-Ming LIN, Po-Wei LIANG, Chu-Han HSIEH, Chih-Lung CHENG, Po-Chih HUANG
  • Publication number: 20220037169
    Abstract: A gas flow accelerator may include a body portion, and a tapered body portion including a first end integrally formed with the body portion. The gas flow accelerator may include an inlet port connected to the body portion and to receive a process gas to be removed from a semiconductor processing tool by a main pumping line. The semiconductor processing tool may include a chuck and a chuck vacuum line to apply a vacuum to the chuck to retain a semiconductor device. The tapered body portion may be configured to generate a rotational flow of the process gas to prevent buildup of processing byproduct on interior walls of the main pumping line. The gas flow accelerator may include an outlet port integrally formed with a second end of the tapered body portion. An end portion of the chuck vacuum line may be provided through the outlet port.
    Type: Application
    Filed: July 31, 2020
    Publication date: February 3, 2022
    Inventors: Sheng-chun YANG, Chih-Lung CHENG, Yi-Ming LIN, Po-Chih HUANG, Yu-Hsiang JUAN, Xuan-Yang ZHENG
  • Publication number: 20210265142
    Abstract: A method for processing semiconductor wafer is provided. The method includes loading a semiconductor wafer on a top surface of a wafer chuck. The method also includes supplying a gaseous material between the semiconductor wafer and the top surface of the wafer chuck through a first gas inlet port and a second gas inlet port located underneath a fan-shaped sector of the top surface. The method further includes supplying a fluid medium to a fluid inlet port of the wafer chuck and guiding the fluid medium from the fluid inlet port to flow through a number of arc-shaped channels located underneath the fan-shaped sector of the top surface. In addition, the method includes supplying a plasma gas over the semiconductor wafer.
    Type: Application
    Filed: February 25, 2020
    Publication date: August 26, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Chun YANG, Yi-Ming LIN, Po-Wei LIANG, Chu-Han HSIEH, Chih-Lung CHENG, Po-Chih HUANG