Patents by Inventor Po-Chih Tseng

Po-Chih Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240125849
    Abstract: An RF testing method is applied between a testing instrument and multiple devices under test at least including a first DUT and a second DUT. The testing instrument includes a signal generator and a signal analyzer. A sync signal is sent to the testing instrument and the first DUT, so that the first DUT occupies the signal generator to receive a testing signal from the signal generator. The first DUT sends an uplink signal to the signal analyzer based on the testing signal to occupy the signal analyzer for signal analysis at a first point in time. The sync signal is sent to the testing instrument and the second DUT, so that the second DUT occupies the signal generator to receive the testing signal from the signal generator at a second point in time. The first point in time is parallel to the second point in time.
    Type: Application
    Filed: March 8, 2023
    Publication date: April 18, 2024
    Inventors: Jung-Yin CHIEN, Po-Yen TSENG, Pin-Lin HUANG, Wen-Chih CHEN
  • Patent number: 7949194
    Abstract: A method for motion estimation and the apparatus thereof are provided. The method for motion estimation uses multi-resolution hierarchial search and allows splitting the optimal block mode at the level of the lowest resolution. The method also allows further splitting of blocks during local refinement at levels of higher resolutions.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: May 24, 2011
    Assignee: Novatek Microelectronics Corp.
    Inventors: Chao-Tsung Huang, Po-Chih Tseng
  • Patent number: 7782952
    Abstract: An apparatus for motion estimation which supports multiple video compression standards and the method thereof is provided. The apparatus uses an interpolation filter with fixed coefficients. The apparatus also adjusts block sizes and calculation details of cost functions according to various video compression standards. Therefore the apparatus is capable of supporting multiple standards and providing high-quality video compression.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: August 24, 2010
    Assignee: Novatek Microelectronics Corp.
    Inventors: Chao-Tsung Huang, Po-Chih Tseng
  • Publication number: 20070092010
    Abstract: An apparatus for motion estimation which supports multiple video compression standards and the method thereof is provided. The apparatus uses an interpolation filter with fixed coefficients. The apparatus also adjusts block sizes and calculation details of cost functions according to various video compression standards. Therefore the apparatus is capable of supporting multiple standards and providing high-quality video compression.
    Type: Application
    Filed: December 12, 2005
    Publication date: April 26, 2007
    Inventors: Chao-Tsung Huang, Po-Chih Tseng
  • Publication number: 20070019732
    Abstract: A method for motion estimation and the apparatus thereof are provided. The method for motion estimation uses multi-resolution hierarchical search and allows splitting the optimal block mode at the level of the lowest resolution. The method also allows further splitting of blocks during local refinement at levels of higher resolutions.
    Type: Application
    Filed: November 4, 2005
    Publication date: January 25, 2007
    Inventors: Chao-Tsung Huang, Po-Chih Tseng
  • Patent number: 7076515
    Abstract: A flipping algorithm for the hardware realization of Lifting-based DWT, relates a flipping algorithm and hardware architecture for the hardware realization of Lifting-based DWT, by using lifting architecture as starting point, by multiplying the edge of the cutset which is through the multiplier and the basic computing unit by the reciprocal of multiplier coefficient in order to cut off the accumulation effect of timing delay. And separating the computing node of said basic computing units into 2 adders then applying flipping architecture to shorten the critical path, therefore not only can keep the merits of Lifting Scheme in hardware requirement but also can shorten the critical path to achieve the optimized hardware architecture.
    Type: Grant
    Filed: August 16, 2002
    Date of Patent: July 11, 2006
    Assignee: National Taiwan University
    Inventors: Liang-Gee Chen, Chao-Tsung Huang, Po-Chih Tseng
  • Publication number: 20040034675
    Abstract: A flipping algorithm for the hardware realization of Lifting-based DWT, relates a flipping algorithm and hardware architecture for the hardware realization of Lifting-based DWT, by using lifting architecture as starting point, by multiplying the edge of the cutset which is through the multiplier and the basic computing unit by the reciprocal of multiplier coefficient in order to cut off the accumulation effect of timing delay.
    Type: Application
    Filed: August 16, 2002
    Publication date: February 19, 2004
    Inventors: Liang-Gee Chen, Chao-Tsung Huang, Po-Chih Tseng