Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) in which a memory structure comprises an inhibition layer inserted between two ferroelectric layers to create a tetragonal-phase dominant ferroelectric structure. In some embodiments, the ferroelectric structure includes a first ferroelectric layer, a second ferroelectric layer overlying the first ferroelectric layer, and a first inhibition layer disposed between the first and second ferroelectric layers and bordering the second ferroelectric layer. The first inhibition layer is a different material than the first and second ferroelectric layers.

Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.

Abstract: A bottom-pinned spin-orbit torque magnetic random access memory (SOT-MRAM) is provided in the present invention, including a substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction (MTJ) on the bottom electrode layer, a spin-orbit torque (SOT) layer on the MTJ, a capping layer on the SOT layer, and an injection layer on the capping layer, wherein the injection layer is divided into individual first part and second part, and the first part and the second part are connected respectively with two ends of the capping layer.

Abstract: A battery pack includes a group of cells, a current path switch coupled to the group of cells, and a current monitoring system. The current monitoring system includes a signal detection unit, a logic unit and a current path control unit. The signal detection unit is coupled to the group of cells and/or a positive terminal of the battery pack, and used to detect at least one voltage signal of the group of cells and/or of the positive terminal of the battery pack. The logic unit is coupled to the signal detection unit, and used to generate a calculated value of a voltage signal of the at least one voltage signal and generate a logic signal according to the calculated value. The current path control unit is coupled to the logic unit and the current path switch, and used to control the current path switch according to the logic signal.

Abstract: A nano-twinned structure on a metallic thin film surface is provided. The nano-twinned structure includes a substrate, an adhesive-lattice-buffer layer over the substrate, and a metallic thin film including Ag, Cu, Au, Pd or Ni over the adhesive-lattice-buffer layer. The bottom region of the metallic thin film has equi-axial coarse grains. The surface region of the metallic thin film contains parallel-arranged high-density twin boundaries (?3+?9) with a pitch from 1 nm to 100 nm. The quantity of the parallel-arranged twin boundaries is 50% to 80% of the total quantity of twin boundaries in the cross-sectional view of the metallic thin film. The parallel-arranged twin boundaries include 30% to 90% [111] crystal orientation. The nano-twinned structure on the metallic thin film surface is formed through a post-deposition ion bombardment on the evaporated metallic thin film surface after the evaporation process.

Abstract: A metallic nano-twinned thin film structure and a method for forming the same are provided. The metallic nano-twinned thin film structure includes a substrate, an adhesive-lattice-buffer layer over the substrate, and a single-layer or multi-layer metallic nano-twinned thin film over the adhesive-lattice-buffer layer. The metallic nano-twinned thin film includes parallel-arranged twin boundaries (?3+?9). In a cross-sectional view of the metallic nano-twinned thin film, the parallel-arranged twin boundaries account for 30% to 90% of total twin boundaries. The parallel-arranged twin boundaries include 80% to 99% of crystal orientation [111]. The single-layer metallic nano-twinned thin film includes copper, gold, palladium or nickel. The multi-layer metallic nano-twinned thin films are respectively composed of silver, copper, gold, palladium or nickel.

Abstract: A method for forming a bonding structure is provided, including providing a first metal, wherein the first metal has a first absolute melting point. The method includes forming a silver nano-twinned layer on the first metal. The silver nano-twinned layer includes parallel-arranged twin boundaries. The parallel-arranged twin boundaries include 90% or more [111] crystal orientation. The method includes oppositely bonding the silver nano-twinned layer to a second metal. The second metal has a second absolute melting point. The bonding of the silver nano-twinned layer and the second metal is performed at a temperature of 300° C. to half of the first absolute melting point or 300° C. to half of the second absolute melting point.

Abstract: A silver nano-twinned thin film structure and a method for forming the same are provided. A silver nano-twinned thin film structure, including: a substrate; an adhesive-lattice-buffer layer over the substrate; and a silver nano-twinned thin film over the adhesive-lattice-buffer layer, wherein the silver nano-twinned thin film comprises parallel-arranged twin boundaries, and a cross-section of the silver nano-twinned thin film reveals that 50% or more of all twin boundaries are parallel-arranged twin boundaries, wherein the parallel-arranged twin boundaries include ?3 and ?9 boundaries, wherein the ?3 and ?9 boundaries include 95% or more crystal orientation.

Abstract: A silver nano-twinned thin film structure and a method for forming the same are provided. A silver nano-twinned thin film structure, including: a substrate; an adhesive-lattice-buffer layer over the substrate; and a silver nano-twinned thin film over the adhesive-lattice-buffer layer, wherein the silver nano-twinned thin film comprises parallel-arranged twin boundaries, and a cross-section of the silver nano-twinned thin film reveals that 50% or more of all twin boundaries are parallel-arranged twin boundaries, wherein the parallel-arranged twin boundaries include ? 3 and ?9 boundaries, wherein the ?3 and ?9 boundaries include 95% or more crystal orientation.

Abstract: Disclosed are an image calibration method and an image calibration apparatus. The image calibration method is adapted to the image calibration apparatus. The image calibration method includes: step (A): capturing an input image having a calibration pattern, wherein the calibration pattern includes at least one frame and an analysis block, the analysis block is surrounded by the frame, and the analysis block includes a plurality of characteristic patterns separated from each other; step (B): determining whether at least one frame is within the input image; step (C): capturing the analysis block when the at least one frame is within the input image; and step (D): executing one of a displacement calibration, a scaling ratio, a rotation calibration, a keystone calibration or a combination thereof for the input image according to positions of the characteristic patterns within the analysis block to generate an output image.

Abstract: Disclosed are an image calibration method and an image calibration apparatus. The image calibration method is adapted to the image calibration apparatus. The image calibration method includes: step (A): capturing an input image having a calibration pattern, wherein the calibration pattern includes at least one frame and an analysis block, the analysis block is surrounded by the frame, and the analysis block includes a plurality of characteristic patterns separated from each other; step (B): determining whether at least one frame is within the input image; step (C): capturing the analysis block when the at least one frame is within the input image; and step (D): executing one of a displacement calibration, a scaling ratio, a rotation calibration, a keystone calibration or a combination thereof for the input image according to positions of the characteristic patterns within the analysis block to generate an output image.

Abstract: The disclosure is related to a method and a system for estimating a stock level of a shelf. An image processing technique is incorporated to conduct stock estimation that is used as a reference for replenishment decisions. In the method, a camera is used to capture a shelf image. The shelf image is divided into multiple sub-region images. Multiple binarized images with respect to the multiple sub-region images are obtained by applying a binarization method. A ratio of the binarization values with respect to the pixels within every sub-region is calculated. The method also includes comparing the ratio of the binarization values in at least two sub-regions with a reference ratio in the at least two sub-regions within a shelf reference image. The comparison is used to estimate the stock level, and also to determine whether the shelf is to be replenished.

Abstract: A memory system includes a first memory bank, a first path selector, a second memory bank, a second path selector, and a sensing device. The first memory bank includes a plurality of first memory cells. The second memory bank includes a plurality of second memory cells. The first path selector includes a plurality of input terminals coupled to the first memory cells through a plurality of first bit lines, and two output terminals. The second path selector includes a plurality of input terminals coupled to the second memory cells through a plurality of second bit lines, and two output terminals. The sensing device is coupled to the output terminals of the first bank selector and the second bank selector, and senses the difference between currents outputted from two of the reference current source, and the terminals of the two bank selectors according to the required operations.

Abstract: The disclosure is related to a method and a system for estimating a stock level of a shelf. An image processing technique is incorporated to conduct stock estimation that is used as a reference for replenishment decisions. In the method, a camera is used to capture a shelf image. The shelf image is divided into multiple sub-region images. Multiple binarized images with respect to the multiple sub-region images are obtained by applying a binarization method. A ratio of the binarization values with respect to the pixels within every sub-region is calculated. The method also includes comparing the ratio of the binarization values in at least two sub-regions with a reference ratio in the at least two sub-regions within a shelf reference image. The comparison is used to estimate the stock level, and also to determine whether the shelf is to be replenished.

Abstract: A memory system includes a first memory bank, a first path selector, a second memory bank, a second path selector, and a sensing device. The first memory bank includes a plurality of first memory cells. The second memory bank includes a plurality of second memory cells. The first path selector includes a plurality of input terminals coupled to the first memory cells through a plurality of first bit lines, and two output terminals. The second path selector includes a plurality of input terminals coupled to the second memory cells through a plurality of second bit lines, and two output terminals. The sensing device is coupled to the output terminals of the first bank selector and the second bank selector, and senses the difference between currents outputted from two of the reference current source, and the terminals of the two bank selectors according to the required operations.

Abstract: A circuit having an external test voltage includes an amplifier, a first P-type metal-oxide-semiconductor transistor, a second P-type metal-oxide-semiconductor transistor, at least one reference resistor, at least one test resistor, a first upper resistor, a second upper resistor and a lower resistor. The second P-type metal-oxide-semiconductor transistor is the same as the first P-type metal-oxide-semiconductor transistor. A difference between a voltage of a test output terminal of each test resistor and a voltage of a reference output terminal of a corresponding reference resistor is kept at a predetermined value by duplicating a current flowing through the first P-type metal-oxide-semiconductor transistor to the second P-type metal-oxide-semiconductor transistor, and feeding an external test voltage to a second terminal of the second upper resistor.

Abstract: A vehicle monitoring system includes a wireless peripheral sensor and a vehicle monitoring device. The vehicle monitoring device includes a vehicle monitoring module and a short-range wireless communication module. The short-range wireless communication module is used to perform short-range data communication with the wireless peripheral sensor, so as to achieve the short-range wireless communication and control between the vehicle monitoring device and wireless peripheral sensor.

Abstract: A circuit having an external test voltage includes an amplifier, a first P-type metal-oxide-semiconductor transistor, a second P-type metal-oxide-semiconductor transistor, at least one reference resistor, at least one test resistor, a first upper resistor, a second upper resistor and a lower resistor. The second P-type metal-oxide-semiconductor transistor is the same as the first P-type metal-oxide-semiconductor transistor. A difference between a voltage of a test output terminal of each test resistor and a voltage of a reference output terminal of a corresponding reference resistor is kept at a predetermined value by duplicating a current flowing through the first P-type metal-oxide-semiconductor transistor to the second P-type metal-oxide-semiconductor transistor, and feeding an external test voltage to a second terminal of the second upper resistor.

Abstract: An image data processing method to capture still images while capturing motion images is disclosed. The method includes stopping a motion image capturing according to a first instruction to generate a first motion image data with a first resolution, thereafter, carrying out live view at a predetermined time; outputting the image data in the predetermined time and generating a first temporal motion data with a second resolution; capturing a still image data according to a second instruction after the predetermined time; transforming the first temporal motion data and the still image data and generating a second motion image data by combining the transformed data with the first motion image data. The method and device according to the present invention can be used in a camera to capture still images while capturing motion images.

Abstract: An image data processing method to capture still images while capturing motion images is disclosed. The method includes stopping a motion image capturing according to a first instruction to generate a first motion image data with a first resolution, thereafter, carrying out live view at a predetermined time; outputting the image data in the predetermined time and generating a first temporal motion data with a second resolution; capturing a still image data according to a second instruction after the predetermined time; transforming the first temporal motion data and the still image data and generating a second motion image data by combining the transformed data with the first motion image data. The method and device according to the present invention can be used in a camera to capture still images while capturing motion images.