Abstract: A self-driven microfluidic chip for rapid influenza A detection is provided. The chip includes: a substrate, a hydrophobic layer, a hydrophilic film layer, and a channel structure layer laminated sequentially. The structure of the channel structure layer includes a plurality of channels, a plurality of valves and reaction chambers in the channels, and a plurality of openings, wherein the hydrophilic film layer includes a pattern corresponding to the structure of the channel structure layer, and forms a disconnected area corresponding to the location of the valves to make the valves hydrophobic; the channel structure layer is formed of a flexible material, and heights of the valves are higher than those of the channels in a thickness direction of the channel structure layer in order to control liquid flow by pressing the valves.

Abstract: A predictive successive approximation register analog-to-digital conversion device and method are provided. A difference between two input signals of a comparator is detected according to a threshold less than or equal to ½ of a voltage increment represented by one least significant bit (LSB). When a difference between a first analog signal and a second analog signal is less than a threshold, a detection circuit enables a bit in a digital signal corresponding to a comparison cycle to which the difference belongs to be forcedly decided to be a first value and predicts values of the remaining bits.

Abstract: A successive approximation analog-to-digital converter (SAR ADC) includes a capacitor array and a comparator. The capacitor array has M capacitors which are arranged to perform capacitor switching operations sequentially, wherein a sum of capacitance values of the M capacitors is equal to (2N?1) unit capacitors, M>N, and M and N are both positive integers. The comparator is arranged for comparing an output of the capacitor array and an analog input sequentially.

Abstract: A successive approximation (SAR) analog-to-digital converter for generating a digital signal of N bits is provided. The converter includes a capacitive digital-to-analog conversion circuit including an (N?1)-th conversion unit to a first conversion unit. Each of the first conversion unit to the (N?2)-th conversion unit includes a capacitor. The (N?1)-th conversion unit comprises a number of sub-capacitors. Each of the sub-capacitors of the (N?1)-th conversion unit has substantially the same capacitance with corresponding capacitor of the first conversion unit to the (N?2)-th conversion unit. During the conversion process, the SAR control circuit, after generating the value of the most significant bit (MSB) of the digital signal, generates the value of the next bit by controlling the (N?1)-th conversion unit. Then, the SAR control circuit repeatedly uses at least one of the sub-capacitors of the (N?1)-th conversion unit to generate the value of other bits to perform self linear compensation.

Abstract: A successive approximation (SAR) analog-to-digital converter for generating a digital signal of N bits is provided. The converter includes a capacitive digital-to-analog conversion circuit including an (N?1)-th conversion unit to a first conversion unit. Each of the first conversion unit to the (N?2)-th conversion unit includes a capacitor. The (N?1)-th conversion unit comprises a number of sub-capacitors. Each of the sub-capacitors of the (N?1)-th conversion unit has substantially the same capacitance with corresponding capacitor of the first conversion unit to the (N?2)-th conversion unit. During the conversion process, the SAR control circuit, after generating the value of the most significant bit (MSB) of the digital signal, generates the value of the next bit by controlling the (N?1)-th conversion unit. Then, the SAR control circuit repeatedly uses at least one of the sub-capacitors of the (N?1)-th conversion unit to generate the value of other bits to perform self linear compensation.

Abstract: A predictive successive approximation register analog-to-digital conversion device and method are provided. A difference between two input signals of a comparator is detected according to a threshold less than or equal to 1/2 of a voltage increment represented by one least significant bit (LSB). When a difference between a first analog signal and a second analog signal is less than a threshold, a detection circuit enables a bit in a digital signal corresponding to a comparison cycle to which the difference belongs to be forcedly decided to be a first value and predicts values of the remaining bits.

Abstract: A successive approximation analog-to-digital converter (SAR ADC) includes a capacitor array and a comparator. The capacitor array has M capacitors which are arranged to perform capacitor switching operations sequentially, wherein a sum of capacitance values of the M capacitors is equal to (2N?1) unit capacitors, M>N, and M and N are both positive integers. The comparator is arranged for comparing an output of the capacitor array and an analog input sequentially.

Abstract: An amplifier circuit includes an amplifier and a noise suppression block. The amplifier is arranged for receiving an input signal at an input port and generating an output signal at an output port according to the input signal. The noise suppression block is coupled between the input port and the output port of the amplifier, and arranged for receiving the input signal and the output signal and applying noise suppression to the output signal generated from the amplifier according to the received input signal and the received output signal.

Abstract: An amplifier circuit includes an amplifier and a noise suppression block. The amplifier is arranged for receiving an input signal at an input port and generating an output signal at an output port according to the input signal. The noise suppression block is coupled between the input port and the output port of the amplifier, and arranged for receiving the input signal and the output signal and applying noise suppression to the output signal generated from the amplifier according to the received input signal and the received output signal.

Abstract: A single-phase down-converter includes a mixer and a local oscillator (LO) signal generator. The mixer is arranged to generate a mixer output signal by mixing a radio frequency (RF) signal and an LO signal. The LO signal generator is coupled to the mixer, and arranged to generate the LO signal with a frequency shifted from an RF carrier frequency by a specific intermediate frequency, wherein when image interference exists, the specific intermediate frequency makes the image interference translated to guard band(s) of channel(s).

Abstract: A control system for dynamically adjusting an output voltage of a voltage converter includes a signal calculation circuit, a pulse width modulator, a voltage converter, a nonlinear calibration circuit and a signal converter. The signal calculation circuit, the pulse width modulator, the voltage converter and the signal converter form a long-tail loop. The signal calculation circuit simultaneously receives a target value and a detection value from the signal converter to generate an error value for adjusting the output of the pulse width modulator. The voltage converter and the nonlinear calibration circuit form a local pulse-squashing loop. Pulse widths of an input signal to the voltage converter can be timely and effectively calibrated and controlled, thereby decreasing power consumption of the voltage converter and providing an effective protective mechanism.

Abstract: A control system for dynamically adjusting an output voltage of a voltage converter includes a signal calculation circuit, a pulse width modulator, a voltage converter, a nonlinear calibration circuit and a signal converter. The signal calculation circuit, the pulse width modulator, the voltage converter and the signal converter form a long-tail loop. The signal calculation circuit simultaneously receives a target value and a detection value from the signal converter to generate an error value for adjusting the output of the pulse width modulator. The voltage converter and the nonlinear calibration circuit form a local pulse-squashing loop. Pulse widths of an input signal to the voltage converter can be timely and effectively calibrated and controlled, thereby decreasing power consumption of the voltage converter and providing an effective protective mechanism.

Abstract: The present invention discloses an on-line calibration method, which utilizes two calibration algorithms running in the background without interrupting the normal operation of the analog signal process. The method includes performing a residue amplifier gain error calibration and performing a DAC non-linearity calibration. The residue amplifier gain error calibration can reduce the gain error of the residue amplifier for a missing code or a missing decision level phenomenon. The DAC non-linearity calibration can relax the matching requirement of passive components in current semiconductor processes. The present invention discloses a two-step ADC (Analog-to-Digital Converter), which includes a first signal processing unit, a second signal processing unit, a programmable gain control unit and a programmable reference voltage generator, performing the on-line calibration method.

Abstract: The present invention discloses an on-line calibration method, which utilizes two calibration algorithms running in the background without interrupting the normal operation of the analog signal process. The method includes performing a residue amplifier gain error calibration and performing a DAC non-linearity calibration. The residue amplifier gain error calibration can reduce the gain error of the residue amplifier for a missing code or a missing decision level phenomenon. The DAC non-linearity calibration can relax the matching requirement of passive components in current semiconductor processes. The present invention discloses a two-step ADC (Analog-to-Digital Converter), which includes a first signal processing unit, a second signal processing unit, a programmable gain control unit and a programmable reference voltage generator, performing the on-line calibration method.

Abstract: A transceiver includes a transmitter, a receiver, and an electrical feedback line. The transmitter has a quadrature-modulator and is configurable to compensate inphase/quadrature phase imbalances produced by hardware of the transmitter. The quadrature-modulator is configured to quadrature-modulate a carrier wave. The receiver has a quadrature-demodulator and is configurable to compensate for inphase/quadrature phase imbalances produced by hardware in the receiver. The quadrature-demodulator is configured to demodulate a quadrature-demodulated carrier. The electrical feedback line connects an output of the transmitter to an input of the receiver.

Abstract: A digital-to-analog converter (DAC) for use in high-speed wireless communications. The DAC of the invention comprises a plurality of current steering cells to bi-directionally provide a differential current output. When the DAC sets the differential current output to zero for example, each of the current steering cells establishes dummy branches between a pair of current sources and thereby prevents the current sources from floating. This in turn enables the DAC to operate with a higher update rate.

Abstract: A differential to single-ended converter, which is composed of a transconductance amplifier, a current mirror and buffer circuit and a transimpedance stage, is disclosed. A differential voltage signal is provided to the inputs of the transconductance amplifier and converted to a differential current signal. The current mirror and buffer circuit serves as a differential to single-ended current conveyer and isolates the transconductance stage and the following transimpedance stage. Finally, the single-ended current signal is provided to the input of the transimpedance stage and converted to a single-ended current signal.

Abstract: A differential to single-ended converter, which is composed of a transconductance amplifier, a current mirror and buffer circuit and a transimpedance stage, is disclosed. A differential voltage signal is provided to the inputs of the transconductance amplifier and converted to a differential current signal. The current mirror and buffer circuit serves as a differential to single-ended current conveyer and isolates the transconductance stage and the following transimpedance stage. Finally, the single-ended current signal is provided to the input of the transimpedance stage and converted to a single-ended current signal.

Abstract: A relay-race FLL/PLL high-speed timing acquisition device according to the invention comprises a transition detector, a voltage controlled oscillator, a loop filter of PLL, a first lowpass filter, a 90.degree. phase shifter, a second lowpass filter, and a plurality of multipliers. In addition, this relay-race FLL/PLL high-speed timing acquisition device is characterized by further comprising a frequency delimiter which includes a highpass filter coupled to a first circuit, a second circuit coupled to the highpass filter, a third lowpass filter coupled to the second circuit, a Schmitt inverter coupled to the third lowpass filter, and a switch member coupled to the Schmitt inverter. The relay-race FLL/PLL high-speed timing acquisition device can obtain stable and high speed timing acquisition by means of the frequency delimiter.

Abstract: A fully differential, wide-band transconductance-transimpedance amplifier with a tuneable gain is disclosed. The amplifier includes a transconductance stage for generating a current signal from an inputted voltage signal. The amplifier also has a current gain stage for amplifying the current signal generated by the transconductance stage. Additionally, the amplifier includes a transimpedance stage for generating an output voltage signal from the amplified current signal generated in the current gain stage.