Abstract: An apparatus and method for expanding a box blank into a box, the apparatus comprising an arm assembly, a controller, a camera and a box blank conveyor. The arm assembly includes a folding arm having a position in a first direction and a rotational angle controlled by the controller based on a position of a feature of the box blank in the field of view of the camera. The camera captures images of the box blank which are used to position the arm assembly and to evaluate the need to reject a box blank.

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain (S/D) region and a contact. The S/D region is located in the substrate and on a side of the gate structure. The contact lands on and connected to the S/D region. The contact wraps around the S/D region.

Abstract: An apparatus and method for expanding a box blank into a box, the apparatus comprising an arm assembly, a controller, a camera and a box blank conveyor. The arm assembly includes a folding arm having a position in a first direction and a rotational angle controlled by the controller based on a position of a feature of the box blank in the field of view of the camera. The camera captures images of the box blank which are used to position the arm assembly and to evaluate the need to reject a box blank.

Abstract: A trench-gate transistor device includes a substrate and a transistor structure. The transistor structure includes a plurality of superjunctions arranged in a first direction, a rectifying area that has at least one Schottky-based diode, and at least one active unit that is located at a side of said rectifying area in a second direction that intersects with the first direction.

Abstract: A transistor production method includes etching a semiconductor substrate to form at least one upper trench portion, sequentially depositing first and second insulating materials over the substrate and partially removing the second insulating material, etching the substrate to form a lower trench portion, depositing a third insulating material over the substrate, disposing a polycrystalline silicon (pc-Si) material in the trench portions and partially removing such material, depositing a fourth insulating material over the substrate and partially removing the third and fourth insulating materials, removing the second insulating material and disposing another pc-Si material in the upper trench portion, and forming a well and a source on the substrate. A trench power transistor thus produced is also disclosed.

Abstract: A trench power transistor includes a semiconductor body having opposite first and second surfaces, and including at least one active region. Such region includes a trench electrode structure, a well, and a source. The trench electrode structure has an electrode trench recessed from the first surface, and includes first, second, and third insulating layers sequentially disposed over bottom and surrounding walls of the electrode trench, a shield electrode enclosed by the third insulating layer, a fourth insulating layer disposed on the first, second, and third insulating layers, and a gate electrode surrounded by the fourth insulating layer. The second insulating layer made of a nitride material and the fourth insulating layer are different in material. A production method of the transistor is also disclosed.

Abstract: A trench power transistor includes a semiconductor body having opposite first and second surfaces, and including at least one active region. Such region includes a trench electrode structure, a well, and a source. The trench electrode structure has an electrode trench recessed from the first surface, and includes first, second, and third insulating layers sequentially disposed over bottom and surrounding walls of the electrode trench, a shield electrode enclosed by the third insulating layer, a fourth insulating layer disposed on the first, second, and third insulating layers, and a gate electrode surrounded by the fourth insulating layer. The second insulating layer made of a nitride material and the fourth insulating layer are different in material. A production method of the transistor is also disclosed.

Abstract: A transistor production method includes etching a semiconductor substrate to form at least one upper trench portion, sequentially depositing first and second insulating materials over the substrate and partially removing the second insulating material, etching the substrate to form a lower trench portion, depositing a third insulating material over the substrate, disposing a polycrystalline silicon (pc-Si) material in the trench portions and partially removing such material, depositing a fourth insulating material over the substrate and partially removing the third and fourth insulating materials, removing the second insulating material and disposing another pc-Si material in the upper trench portion, and forming a well and a source on the substrate. A trench power transistor thus produced is also disclosed.

Abstract: A double gate trench power transistor and manufacturing method thereof are provided. The double gate trench power transistor gate structure includes an epitaxial layer, a trench structure formed in the epitaxial layer, at least two gate structures, and a shielding electrode structure. The trench structure includes a deep trench portion and two shallow trench portions respectively adjacent to two opposite sides of the deep trench portion. Each of the gate structures formed in each of the shallow trench portions includes a gate insulating layer and a gate electrode. The gate insulating layer has a first dielectric layer, a second dielectric layer and a third dielectric layer. The second dielectric layer is interposed between the first and third dielectric layers. Additionally, a portion of the gate insulating layer is in contact with a shielding dielectric layer of the shielding electrode structure.

Abstract: A trench power semiconductor device is provided. A trench gate structure of the trench power semiconductor device located in a cell trench of an epitaxial layer includes a first dielectric layer, a second dielectric layer, a gate electrode, a third dielectric layer, and a shielding layer. The second dielectric layer is interposed between the first and third dielectric layers, and the second dielectric layer is made from different material than the first dielectric layer. After performing a selective etching step on the second dielectric layer, a recess can be formed among the first, second and third dielectric layers. The gate electrode includes a conductive layer formed in the recess region, and the shielding electrode is surrounded by the third dielectric layer and insulated from the conductive layer.

Abstract: A trench power semiconductor device is provided. A trench gate structure of the trench power semiconductor device located in a cell trench of an epitaxial layer includes a first dielectric layer, a second dielectric layer, a gate electrode, a third dielectric layer, and a shielding layer. The second dielectric layer is interposed between the first and third dielectric layers, and the second dielectric layer is made from different material than the first dielectric layer. After performing a selective etching step on the second dielectric layer, a recess can be formed among the first, second and third dielectric layers. The gate electrode includes a conductive layer formed in the recess region, and the shielding electrode is surrounded by the third dielectric layer and insulated from the conductive layer.

Abstract: A trenched power semiconductor element, a trenched-gate structure thereof being in an element trench of an epitaxial layer and including at least a shielding electrode, a shielding dielectric layer, a gate electrode, an insulating separation layer, and a gate insulating layer. The shielding electrode is disposed at the bottom of the element trench, the shielding dielectric layer is disposed at a lower portion of the element trench, surrounding the shielding electrode to separate the shielding electrode from the epitaxial layer, wherein the top portion of the shielding dielectric layer includes a hole. The gate electrode is disposed above the shielding electrode, being separated from the hole at a predetermined distance through the insulating separation layer. The insulating separation layer is disposed between the shielding dielectric layer and the gate electrode layer to seal the hole.

Abstract: A trench power transistor is provided. The trench gate structure of the trench power transistor includes at least one insulting layer, a gate electrode, and a shielding electrode, which are disposed in a trench of an epitaxial layer. The insulating layer formed on an inner wall of the active trench to isolate an epitaxial layer from the gate and the shielding electrodes. The insulating layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer. The first and second dielectric layers extend from an upper portion of the inner wall to a lower portion of the inner wall of the active trench. The third dielectric layer is formed on the second dielectric layer and located at the lower portion of the active trench. A portion of the second dielectric layer is interposed between the first and third dielectric layers.

Abstract: A trench power transistor is provided. The trench gate structure of the trench power transistor includes at least one insulting layer, a gate electrode, and a shielding electrode, which are disposed in a trench of an epitaxial layer. The insulating layer formed on an inner wall of the active trench to isolate an epitaxial layer from the gate and the shielding electrodes. The insulating layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer. The first and second dielectric layers extend from an upper portion of the inner wall to a lower portion of the inner wall of the active trench. The third dielectric layer is formed on the second dielectric layer and located at the lower portion of the active trench. A portion of the second dielectric layer is interposed between the first and third dielectric layers.

Abstract: A double gate trench power transistor and manufacturing method thereof are provided. The double gate trench power transistor gate structure includes an epitaxial layer, a trench structure formed in the epitaxial layer, at least two gate structures, and a shielding electrode structure. The trench structure includes a deep trench portion and two shallow trench portions respectively adjacent to two opposite sides of the deep trench portion. Each of the gate structures formed in each of the shallow trench portions includes a gate insulating layer and a gate electrode. The gate insulating layer has a first dielectric layer, a second dielectric layer and a third dielectric layer. The second dielectric layer is interposed between the first and third dielectric layers. Additionally, a portion of the gate insulating layer is in contact with a shielding dielectric layer of the shielding electrode structure.

Abstract: A power semiconductor device having low on-state resistance includes a substrate having an epitaxial layer formed thereon, a gate structure, a termination structure, and a patterned conductive layer. The epitaxial layer has at least a first trench and a second trench. The gate structure is embedded in the first trench, including a gate electrode and a shielding electrode disposed under the gate electrode. The termination structure is embedded in the second trench, including a termination electrode. The patterned conductive layer is disposed above the epitaxial layer. Specially, the shield electrode of the gate structure and the termination electrode of the termination structure are configured to receive the gate voltage. The patterned conductive layer is configured to electrically contact said gate electrode and termination electrodes by a first contact plug and a second contact plug respectively.

Abstract: A power semiconductor device having low on-state resistance includes a substrate having an epitaxial layer formed thereon, a gate structure, a termination structure, and a patterned conductive layer. The epitaxial layer has at least a first trench and a second trench. The gate structure is embedded in the first trench, including a gate electrode and a shielding electrode disposed under the gate electrode. The termination structure is embedded in the second trench, including a termination electrode. The patterned conductive layer is disposed above the epitaxial layer. Specially, the shield electrode of the gate structure and the termination electrode of the termination structure are configured to receive the gate voltage. The patterned conductive layer is configured to electrically contact said gate electrode and termination electrodes by a first contact plug and a second contact plug respectively.

Abstract: A semiconductor structure of a trench power device comprises a base, an insulating layer, and a source conductive layer. The base includes a first trench etched from the top surface thereof, and two portions of the top surface arranged at two opposite sides of the first trench are respectively defined as two top contacting surfaces. Part of the first trench is filled with the insulating layer, and two inner walls of a non-filled portion of the first trench are respectively defined as two side contacting surfaces without contacting the insulating layer. The source conductive layer is embedded in the insulating layer. Thus, when a metallic layer is integrally formed on the semiconductor structure and connects the top contacting surfaces and the side contacting surfaces, the top contacting surfaces and the side contacting surfaces are configured to be a Schottky barrier interface.

Abstract: A trench power device includes a semiconductor layer, a trench gate structure, a trench source structure, and a contact. The semiconductor layer has an epitaxial layer, a doped body region, a S/D region, and a doped contact-carrying region. The doped body region is formed in the epitaxial layer, the S/D region is formed in the doped body region, and the doped contact-carrying region is formed in the doped body region and outside a projecting portion defined by orthogonally projecting from the S/D region to the doped body region. The trench gate structure is embedded in the S/D region, the doped body region, and the epitaxial layer. The trench source structure is embedded in the doped body region and the epitaxial layer, and is connected to the doped contact-carrying region. The contact is connected to the S/D region and the doped contact-carrying region.

Abstract: An object of this invention is to provide a Schottky diode structure to increase the contact area at a Schottky junction between the Schottky Barrier metal and a semiconductor substrate. The larger contact area of the Schottky junction is, the lower of the forward voltage drop across the Schottky diode will be, thereby improving the performance and efficiency of the Schottky diode. The present invention also discloses that a plurality of trenches with adjacent top mesas can be used to form a Schottky diode with even larger contact area, wherein the trenches are built using the isolation area between two cells of MOSFET with minimum extra overhead by shrinking the dimension of pitch between two trenches.