Patents by Inventor Po-hsun Ho

Po-hsun Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230387252
    Abstract: Methods for making transistors with a semiconducting monolayer and low contact resistance are disclosed. The source/drain terminals are on opposite sides of the semiconducting monolayer from the gate terminal. The contact and/or spacer regions of the semiconducting monolayer are covered with a dopant layer on the surface opposite the source/drain terminals. The gate dielectric layer directly contacts the semiconducting monolayer. The resulting structure maintains high mobility in the semiconducting layer and has low contact resistance.
    Type: Application
    Filed: May 27, 2022
    Publication date: November 30, 2023
    Inventor: Po-Hsun Ho
  • Publication number: 20230369042
    Abstract: Methods for making transistors with a semiconducting monolayer are disclosed. The semiconducting monolayer is covered with a hexagonal boron nitride (hBN) monolayer. A thin gate dielectric layer can then be formed upon the hBN monolayer using a plasma-enhanced deposition process, without the semiconducting monolayer being damaged by the plasma. The resulting structure maintains high mobility in the semiconducting layer, has improved capacitance, and good heat dissipation.
    Type: Application
    Filed: May 16, 2022
    Publication date: November 16, 2023
    Inventor: Po-Hsun Ho
  • Publication number: 20230282739
    Abstract: A device includes a first source/drain region including: a first metal layer including a first metal; and a conductive two-dimensional material on the first metal layer; an isolation layer physically contacting a sidewall of the first metal layer, wherein the conductive two-dimensional material protrudes above the isolation layer; a two-dimensional semiconductor material on the isolation layer, wherein a sidewall of the two-dimensional semiconductor material physically contacts a sidewall of the conductive two-dimensional material; and a gate stack on the two-dimensional semiconductor material.
    Type: Application
    Filed: May 13, 2022
    Publication date: September 7, 2023
    Inventor: Po-Hsun Ho
  • Publication number: 20140158988
    Abstract: Disclosed is a graphene transistor. The graphene transistor includes a source electrode, a drain electrode, a graphene layer, an insulating layer, a gate electrode and at least one doping layer. The graphene layer is disposed between the source electrode and the drain electrode. The gate electrode is separated from the graphene layer, the source electrode and the drain electrode by the insulating layer. The doping layer is disposed on the graphene layer or beneath the graphene layer for providing dopants for the graphene layer. The doping layer includes nonstoichiometric compounds. The graphene transistor of the present invention has a superior air stability and is not easily affected by environment.
    Type: Application
    Filed: June 5, 2013
    Publication date: June 12, 2014
    Inventors: Chun-wei Chen, Po-hsun Ho