Patents by Inventor Po-Kang Ho
Po-Kang Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11978676Abstract: A device includes a first semiconductor fin extending from a substrate, a second semiconductor fin extending from the substrate, a dielectric fin over the substrate, a first isolation region between the first semiconductor fin and the dielectric fin, and a second isolation region between the first semiconductor fin and the second semiconductor fin. The first semiconductor fin is disposed between the second semiconductor fin and the dielectric fin. The first isolation region has a first concentration of an impurity. The second isolation region has a second concentration of the impurity. The second concentration is less than the first concentration. A top surface of the second isolation region is disposed closer to the substrate than a top surface of the first isolation region.Type: GrantFiled: February 7, 2022Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Szu-Ying Chen, Po-Kang Ho, Sen-Hong Syue, Huicheng Chang, Yee-Chia Yeo
-
Publication number: 20240096897Abstract: In an embodiment, a device includes: a first semiconductor fin extending from a substrate; a second semiconductor fin extending from the substrate; a hybrid fin over the substrate, the second semiconductor fin disposed between the first semiconductor fin and the hybrid fin; a first isolation region between the first semiconductor fin and the second semiconductor fin; and a second isolation region between the second semiconductor fin and the hybrid fin, a top surface of the second isolation region disposed further from the substrate than a top surface of the first isolation region.Type: ApplicationFiled: December 1, 2023Publication date: March 21, 2024Inventors: Po-Kang Ho, Tsai-Yu Huang, Huicheng Chang, Yee-Chia Yeo
-
Patent number: 11923366Abstract: In an embodiment, a device includes: a first semiconductor fin extending from a substrate; a second semiconductor fin extending from the substrate; a hybrid fin over the substrate, the second semiconductor fin disposed between the first semiconductor fin and the hybrid fin; a first isolation region between the first semiconductor fin and the second semiconductor fin; and a second isolation region between the second semiconductor fin and the hybrid fin, a top surface of the second isolation region disposed further from the substrate than a top surface of the first isolation region.Type: GrantFiled: July 9, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Kang Ho, Tsai-Yu Huang, Huicheng Chang, Yee-Chia Yeo
-
Publication number: 20240030312Abstract: A method includes forming a fin structure over a substrate; depositing a dummy gate layer over the substrate and the fin structure; etching back the dummy gate layer; performing an implantation process to the dummy gate layer to form an implantation region in the dummy gate layer, wherein a vertical thickness of the dummy gate layer is greater than a vertical thickness of the implantation region; forming a patterned hard mask stack over the implantation region; patterning the implantation region and the dummy gate layer by using the patterned hard mask stack as an etch mask to form a dummy gate structure over the fin structure; and replacing the dummy gate structure with a metal gate structure.Type: ApplicationFiled: July 22, 2022Publication date: January 25, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Ju CHEN, Wei-Ting CHANG, Po-Kang HO, Su-Hao LIU, Yee-Chia YEO
-
Publication number: 20230260804Abstract: The method includes performing a well implantation process to dope a dopant into a semiconductor substrate; after performing the well implantation process, performing a flash anneal on the semiconductor substrate, the flash anneal including a first preheat step and a first annealing step after the first preheat step, the first preheat step performed at a preheat temperature ranging from about 200° C. to about 800° C., the first annealing step having a peak temperature ramp profile, the peak temperature ramp profile having a peak temperature ranging from about 1000° C. to about 1200° C.; after performing the flash anneal, performing a rapid thermal anneal (RTA) on the semiconductor substrate, the RTA including a second preheat step, the first preheat step of the flash anneal being performed for a shorter duration than the second preheat step of the RTA.Type: ApplicationFiled: February 15, 2022Publication date: August 17, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jhih-Yong HAN, Wen-Yen CHEN, Po-Kang HO, Tsai-Yu HUANG, Huicheng CHANG, Yee-Chia YEO
-
Publication number: 20230038762Abstract: A device includes a first semiconductor fin extending from a substrate, a second semiconductor fin extending from the substrate, a dielectric fin over the substrate, a first isolation region between the first semiconductor fin and the dielectric fin, and a second isolation region between the first semiconductor fin and the second semiconductor fin. The first semiconductor fin is disposed between the second semiconductor fin and the dielectric fin. The first isolation region has a first concentration of an impurity. The second isolation region has a second concentration of the impurity. The second concentration is less than the first concentration. A top surface of the second isolation region is disposed closer to the substrate than a top surface of the first isolation region.Type: ApplicationFiled: February 7, 2022Publication date: February 9, 2023Inventors: Szu-Ying Chen, Po-Kang Ho, Sen-Hong Syue, Huicheng Chang, Yee-Chia Yeo
-
Publication number: 20230008413Abstract: A method includes forming a fin protruding from a semiconductor substrate; forming a dummy gate stack over the fin, wherein forming the dummy gate stack includes depositing a layer of amorphous material over the fin; performing an anneal process on the layer of amorphous material, wherein the anneal process recrystallizes the layer of amorphous material into a layer of polycrystalline material, wherein the anneal process includes heating the layer of amorphous material for less than one millisecond; and patterning the layer of polycrystalline material; and forming an epitaxial source/drain region in the fin adjacent the dummy gate stack; and removing the dummy gate stack and replacing the dummy gate stack with a replacement gate stack.Type: ApplicationFiled: February 16, 2022Publication date: January 12, 2023Inventors: Po-Kang Ho, Kuo-Ju Chen, Wei-Ting Chang, Wei-Fu Wang, Li-Ting Wang, Huicheng Chang, Yee-Chia Yeo, Yi-Chao Wang, Tsai-Yu Huang
-
Publication number: 20220359517Abstract: In an embodiment, a device includes: a first semiconductor fin extending from a substrate; a second semiconductor fin extending from the substrate; a hybrid fin over the substrate, the second semiconductor fin disposed between the first semiconductor fin and the hybrid fin; a first isolation region between the first semiconductor fin and the second semiconductor fin; and a second isolation region between the second semiconductor fin and the hybrid fin, a top surface of the second isolation region disposed further from the substrate than a top surface of the first isolation region.Type: ApplicationFiled: July 9, 2021Publication date: November 10, 2022Inventors: Po-Kang Ho, Tsai-Yu Huang, Huicheng Chang, Yee-Chia Yeo
-
Publication number: 20220238350Abstract: A semiconductor device is provided. The semiconductor device has a fin structure that protrudes vertically upwards. A lateral dimension of the fin structure is reduced. A semiconductor layer is formed on the fin structure after the reducing of the lateral dimension. An annealing process is performed to the semiconductor device after the forming of the semiconductor layer. A dielectric layer is formed over the fin structure after the performing of the annealing process.Type: ApplicationFiled: April 11, 2022Publication date: July 28, 2022Inventors: Tzung-Yi Tsai, Yen-Ming Chen, Tsung-Lin Lee, Po-Kang Ho
-
Patent number: 11302535Abstract: A semiconductor device is provided. The semiconductor device has a fin structure that protrudes vertically upwards. A lateral dimension of the fin structure is reduced. A semiconductor layer is formed on the fin structure after the reducing of the lateral dimension. An annealing process is performed to the semiconductor device after the forming of the semiconductor layer. A dielectric layer is formed over the fin structure after the performing of the annealing process.Type: GrantFiled: October 12, 2018Date of Patent: April 12, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tzung-Yi Tsai, Yen-Ming Chen, Tsung-Lin Lee, Po-Kang Ho
-
Publication number: 20200006084Abstract: A semiconductor device is provided. The semiconductor device has a fin structure that protrudes vertically upwards. A lateral dimension of the fin structure is reduced. A semiconductor layer is formed on the fin structure after the reducing of the lateral dimension. An annealing process is performed to the semiconductor device after the forming of the semiconductor layer. A dielectric layer is formed over the fin structure after the performing of the annealing process.Type: ApplicationFiled: October 12, 2018Publication date: January 2, 2020Inventors: Tzung-Yi Tsai, Yen-Ming Chen, Tsung-Lin Lee, Po-Kang Ho
-
Patent number: 9893185Abstract: A FinFET including a substrate, a plurality of isolation structures, a plurality of blocking layers, and a gate stack is provided. The substrate has a plurality of semiconductor fins. The isolation structures are located on the substrate to isolate the semiconductor fins. In addition, the semiconductor fins protrude from the isolation structures. The blocking layers are located between the isolation structures and the semiconductor fins. The material of the blocking layers is different from the material of the isolation structures. The gate stack is disposed across portions of the semiconductor fins, portions of the blocking layers and portions of the isolation structures. In addition, a method for fabricating the FinFET is also provided.Type: GrantFiled: February 26, 2016Date of Patent: February 13, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Ta Wu, Yu-Ting Lin, Po-Kai Hsiao, Po-Kang Ho, Ting-Chun Wang
-
Publication number: 20170250282Abstract: A FinFET including a substrate, a plurality of isolation structures, a plurality of blocking layers, and a gate stack is provided. The substrate has a plurality of semiconductor fins. The isolation structures are located on the substrate to isolate the semiconductor fins. In addition, the semiconductor fins protrude from the isolation structures. The blocking layers are located between the isolation structures and the semiconductor fins. The material of the blocking layers is different from the material of the isolation structures. The gate stack is disposed across portions of the semiconductor fins, portions of the blocking layers and portions of the isolation structures. In addition, a method for fabricating the FinFET is also provided.Type: ApplicationFiled: February 26, 2016Publication date: August 31, 2017Inventors: Cheng-Ta Wu, Yu-Ting Lin, Po-Kai Hsiao, Po-Kang Ho, Ting-Chun Wang