Patents by Inventor Po-Ming HUANG
Po-Ming HUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240186412Abstract: A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.Type: ApplicationFiled: February 14, 2024Publication date: June 6, 2024Inventors: Po-Yu Chen, Wan-Hua Huang, Jing-Ying Chen, Kuo-Ming Wu
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Patent number: 11992322Abstract: A heart rhythm detection method and system by using radar sensor is capable of collecting an original signal using a radar sensor toward at least one subject, and converting the original signal to a two dimensional image information (i.e., spectrogram) using the concept of image vision. Then, the neural network automatically learns which heartbeat frequency should be focused on and which heartbeat frequency should be filtered out in the two dimensional image information through deep learning, so that the heartbeat frequencies can be extracted effectively.Type: GrantFiled: March 30, 2021Date of Patent: May 28, 2024Assignee: IONETWORKS INC.Inventors: Jing-Ming Guo, Ting Lin, Chia-Fen Chang, Jeffry Susanto, Yi-Hsiang Lin, Po-Cheng Huang, Yu-Wen Wei
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Publication number: 20240162349Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.Type: ApplicationFiled: January 24, 2024Publication date: May 16, 2024Inventors: Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen
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Patent number: 11972957Abstract: A gas flow accelerator may include a body portion, and a tapered body portion including a first end integrally formed with the body portion. The gas flow accelerator may include an inlet port connected to the body portion and to receive a process gas to be removed from a semiconductor processing tool by a main pumping line. The semiconductor processing tool may include a chuck and a chuck vacuum line to apply a vacuum to the chuck to retain a semiconductor device. The tapered body portion may be configured to generate a rotational flow of the process gas to prevent buildup of processing byproduct on interior walls of the main pumping line. The gas flow accelerator may include an outlet port integrally formed with a second end of the tapered body portion. An end portion of the chuck vacuum line may be provided through the outlet port.Type: GrantFiled: July 31, 2020Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-chun Yang, Chih-Lung Cheng, Yi-Ming Lin, Po-Chih Huang, Yu-Hsiang Juan, Xuan-Yang Zheng
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Publication number: 20240136401Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material and a passivation layer is disposed on the second semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material. A silicide is arranged within the passivation layer and along tops of the first doped region and the second doped region.Type: ApplicationFiled: January 5, 2024Publication date: April 25, 2024Inventors: Yin-Kai Liao, Sin-Yi Jiang, Hsiang-Lin Chen, Yi-Shin Chu, Po-Chun Liu, Kuan-Chieh Huang, Jyh-Ming Hung, Jen-Cheng Liu
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Patent number: 11960253Abstract: A system and a method for parameter optimization with adaptive search space and a user interface using the same are provided. The system includes a data acquisition unit, an adaptive adjustment unit and an optimization search unit. The data acquisition unit obtains a set of executed values of several operating parameters and a target parameter. The adaptive adjustment unit includes a parameter space transformer and a search range definer. The parameter space transformer performs a space transformation on a parameter space of the operating parameters according to the executed values. The search range definer defines a parameter search range in a transformed parameter space based on the sets of the executed values. The optimization search unit takes the parameter search range as a limiting condition and takes optimizing the target parameter as a target to search for a set of recommended values of the operating parameters.Type: GrantFiled: December 28, 2020Date of Patent: April 16, 2024Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Po-Yu Huang, Chun-Fang Chen, Hong-Chi Ku, Te-Ming Chen, Chien-Liang Lai, Sen-Chia Chang
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Publication number: 20240097035Abstract: Epitaxial source/drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs, and methods of fabricating the epitaxial source/drain structures, are disclosed herein. An exemplary device includes a dielectric substrate. The device further includes a channel layer, a gate disposed over the channel layer, and an epitaxial source/drain structure disposed adjacent to the channel layer. The channel layer, the gate, and the epitaxial source/drain structure are disposed over the dielectric substrate. The epitaxial source/drain structure includes an inner portion having a first dopant concentration and an outer portion having a second dopant concentration that is less than the first dopant concentration. The inner portion physically contacts the dielectric substrate, and the outer portion is disposed between the inner portion and the channel layer. In some embodiments, the outer portion physically contacts the dielectric substrate.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Inventors: Chen-Ming Lee, I-Wen Wu, Po-Yu Huang, Fu-Kai Yang, Mei-Yun Wang
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Patent number: 11935950Abstract: A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.Type: GrantFiled: August 23, 2021Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Yu Chen, Wan-Hua Huang, Jing-Ying Chen, Kuo-Ming Wu
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Publication number: 20240086612Abstract: An IC device includes first through third rows of fin field-effect transistors (FinFETs), wherein the second row is between and adjacent to each of the first and third rows, the FinFETs of the first row are one of an n-type or p-type, the FinFETs of the second and third rows are the other of the n-type or p-type, the FinFETs of the first and third rows include a first total number of fins, and the FinFETs of the second row include a second total number of fins one greater or fewer than the first total number of fins.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Inventors: Po-Hsiang HUANG, Fong-Yuan CHANG, Clement Hsingjen WANN, Chih-Hsin KO, Sheng-Hsiung CHEN, Li-Chun TIEN, Chia-Ming HSU
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Publication number: 20240081077Abstract: A transistor includes a first semiconductor layer, a second semiconductor layer, a semiconductor nanosheet, a gate electrode and source and drain electrodes. The semiconductor nanosheet is physically connected to the first semiconductor layer and the second semiconductor layer. The gate electrode wraps around the semiconductor nanosheet. The source and drain electrodes are disposed at opposite sides of the gate electrode. The first semiconductor layer surrounds the source electrode, the second semiconductor layer surrounds the drain electrode, and the semiconductor nanosheet is disposed between the source and drain electrodes.Type: ApplicationFiled: September 1, 2022Publication date: March 7, 2024Applicants: Taiwan Semiconductor Manufacturing Company, Ltd., National Yang Ming Chiao Tung UniversityInventors: Po-Tsun Liu, Meng-Han Lin, Zhen-Hao Li, Tsung-Che Chiang, Bo-Feng Young, Hsin-Yi Huang, Sai-Hooi Yeong, Yu-Ming Lin
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Patent number: 11916146Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.Type: GrantFiled: April 11, 2022Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen
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Patent number: 11133278Abstract: A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, a cap layer, a conductive terminal, and a dam structure. The semiconductor die has a first surface. The cap layer is over the semiconductor die and has a second surface facing the first surface of the semiconductor die. The conductive terminal penetrates the cap layer and electrically connects to the semiconductor die. The dam structure is between the semiconductor die and the cap layer and surrounds a portion of the conductive terminal between the first surface and the second surface, thereby forming a gap between the cap layer and the semiconductor die.Type: GrantFiled: September 25, 2019Date of Patent: September 28, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yu-Che Huang, Ching-Han Huang, An-Nong Wen, Po-Ming Huang
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Publication number: 20200111760Abstract: A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, a cap layer, a conductive terminal, and a dam structure. The semiconductor die has a first surface. The cap layer is over the semiconductor die and has a second surface facing the first surface of the semiconductor die. The conductive terminal penetrates the cap layer and electrically connects to the semiconductor die. The dam structure is between the semiconductor die and the cap layer and surrounds a portion of the conductive terminal between the first surface and the second surface, thereby forming a gap between the cap layer and the semiconductor die.Type: ApplicationFiled: September 25, 2019Publication date: April 9, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yu-Che HUANG, Ching-Han HUANG, An-Nong WEN, Po-Ming HUANG
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Patent number: 9817788Abstract: A hub device and corresponding method include a first chip having at least a first upstream port and a plurality of first downstream ports, a second chip, having at least a second upstream port and at least one second downstream port; and an external memory device, storing firmware data corresponding to the first chip and the second chip. One one of the first downstream ports of the first chip is coupled to the second upstream port of the second chip to form a tiered hub, and the first chip and the second chip are sequentially enabled and the first chip and the second chip sequentially load the corresponding firmware data.Type: GrantFiled: May 27, 2016Date of Patent: November 14, 2017Assignee: VIA TECHNOLOGIES, INC.Inventors: Chih-Long Ho, Yi-Te Chen, Wen-Hao Cheng, Kuo-Yu Wu, Chun-Heng Lin, Po-Ming Huang
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Patent number: 9789528Abstract: An automated forming machine is adapted to form at least one metal sheet and contains: a material supplying zone, a heating zone, a forming zone, and a cooling zone which are all configured to accommodate components of the automated forming machine. The automated forming machine includes: a frame and a forming device for clamping, heating, and blow molding the at least one metal sheet. The automated forming machine also includes plural tracks, plural loading carriers, a first pushing devices, a second pushing device, a third pushing device, a fourth pushing device, a pulling device, a first heating device and two cooling devices, and each cooling device includes a support rack and a plurality of spray nozzles.Type: GrantFiled: August 11, 2015Date of Patent: October 17, 2017Inventor: Po Ming Huang
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Publication number: 20170043387Abstract: An automated forming machine is adapted to form at least one metal sheet and contains: a material supplying zone, a heating zone, a forming zone, and a cooling zone which are all configured to accommodate components of the automated forming machine. The automated forming machine includes: a frame and a forming device for clamping, heating, and blow molding the at least one metal sheet. The automated forming machine also includes plural tracks, plural loading carriers, a first pushing devices, a second pushing device, a third pushing device, a fourth pushing device, a pulling device, a first heating device and two cooling devices, and each cooling device includes a support rack and a plurality of spray nozzles.Type: ApplicationFiled: August 11, 2015Publication date: February 16, 2017Inventor: Po Ming HUANG
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Patent number: 9511404Abstract: A sheet molding device contains: a base, a mold, and at least one spray nozzle. The base includes a forming zone and a removing zone. The mold includes a molding part, an insolation washer, and a sealing part. The molding part has a peripheral rib, a die cavity, and a first heater. The insolation washer has a melting point higher a sheet, and the insolation washer is connected with a top surface of the peripheral rib and its top surface is higher than the peripheral rib. The sealing part has an outlet connecting with a high-pressure gas supply unit via an air pipe and has a second heater. The molding part and the sealing part are connected together in the forming zone, and after blow molding the sheet, the sealing part is moved toward the removing zone. Furthermore, the at least one spray nozzle is arranged in the removing zone.Type: GrantFiled: July 1, 2015Date of Patent: December 6, 2016Inventor: Po Ming Huang
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Publication number: 20160275040Abstract: A hub device and corresponding method include a first chip having at least a first upstream port and a plurality of first downstream ports, a second chip, having at least a second upstream port and at least one second downstream port; and an external memory device, storing firmware data corresponding to the first chip and the second chip. One one of the first downstream ports of the first chip is coupled to the second upstream port of the second chip to form a tiered hub, and the first chip and the second chip are sequentially enabled and the first chip and the second chip sequentially load the corresponding firmware data.Type: ApplicationFiled: May 27, 2016Publication date: September 22, 2016Inventors: Chih-Long HO, Yi-Te CHEN, Wen-Hao CHENG, Kuo-Yu WU, Chun-Heng LIN, Po-Ming HUANG
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Publication number: 20160059467Abstract: A mold structure contains: a first mold, an isolation washer, and a second mold. The first mold includes a ring-shaped closing rib arranged on a top surface thereof and a cavity defined in the closing rib. The isolation washer is formed in a ring shape and includes a melting point higher than a molding plate, wherein when the isolation washer retains with the fixing slot of the closing rib, and a top surface of the isolation washer is higher than that of the closing rib, the molding plate is held by the isolation washer. The second mold moves relative to the first mold to press a top surface of the molding plate, the second mold includes a close chamber defined on a bottom surface thereof and corresponding to the cavity and includes a gas supply pipe communicating with the close chamber and connecting with a high-pressure gas device.Type: ApplicationFiled: August 28, 2014Publication date: March 3, 2016Inventor: PO MING HUANG
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Patent number: 8877319Abstract: A multi-layer composite structure contains metal plates and wooden plates. On a contacting surface of each plate is applied an adhesive. Top surfaces and bottom surfaces of the metal plates are ground by a grinding wheel to form finely concaved patterns. The top surfaces and the bottom surfaces of the metal plates and surfaces of the finely concaved patterns are sandblasted to form plural rough faces which are soaked in a chemical agent to form plural tiny pores, are anodized to generate oxidation, and are back anodized to eliminate oxide. On the top surfaces and the bottom surfaces of the metal plates and the surfaces of the finely concaved patterns are formed plural micro-pores. Thus, when the adhesive is applied on each metal plate and each wooden plate, each metal plate and each wooden plate are stuck together.Type: GrantFiled: July 29, 2013Date of Patent: November 4, 2014Inventor: Po Ming Huang