Abstract: A method of lithography process is provided. The method includes forming a conductive layer over a reticle. The method includes applying ionized particles to the reticle by a discharging device. The method includes forming a photoresist layer over a semiconductor substrate. The method includes securing the semiconductor substrate by a wafer electrostatic-clamp. The method also includes patterning the photoresist layer by emitting radiation from a radiation source via the reticle.

Abstract: A method of forming a memory structure is provided. The method includes providing a substrate, wherein the substrate has a plurality of isolation structures, and the isolation structures include a plurality of first protrusions protruding above the substrate; replacing the first protrusions with a plurality of second protrusions to define a plurality of predetermined regions of floating gates between the second protrusions. The replacing step includes forming an insulation filling material between the first protrusions and on the substrate, and performing a patterning process to the insulation filling and the first protrusions to form second protrusions to define the predetermined regions of the floating gates, and forming a plurality of floating gates in the predetermined regions of the floating gates.

Abstract: A vacuum battery structural assembly and a vacuum multi-cell battery module composed thereof are provided and include a first repeating unit including a first frame plate and a second frame plate with respect to the first frame plate; and an electrolyte channel defined within the first frame plate and the second frame plate to accommodate a liquid electrolyte, wherein both a surface of the first frame plate and a surface of the second frame plate include a vacuum suction area, the vacuum suction area includes a vacuum aperture and a vacuum channel, wherein the vacuum aperture is formed on at least one surface of the first frame plate and the second frame plate, the vacuum channel is positioned inside the first frame plate and the second frame plate, and is configured to generate a longitudinal pressing suction force and seal the first frame plate and the second frame plate.

Abstract: A method of forming the semiconductor device is provided. The method includes following steps. A memory structure is formed over a first conductive line over a substrate and is electrically connected to the first conductive line. A sacrificial layer is formed on the memory structure. A spacer layer is formed to cover the memory structure and the sacrificial layer. A first dielectric layer is formed to cover the spacer layer. A planarization process is performed to remove a portion of the first dielectric layer. A second dielectric layer is formed on the spacer layer and the first dielectric layer. A patterning process is performed to form an opening exposing a portion of the top surface of the sacrificial layer. The sacrificial layer is removed to form a recess. A second conductive line is formed in the opening and the recess to be electrically coupled to the memory structure.

Abstract: A resistive random access memory (RRAM) and its manufacturing method are provided. The RRAM includes bottom contact structures formed in a substrate, memory cells formed on the substrate, and an insulating structure formed between adjacent memory cells. The memory cell includes a bottom electrode layer, two L-shaped resistance switching layers, oxygen ion diffusion barrier layers, and a top electrode layer. The bottom electrode layer is formed on one of the bottom contact structures. The L-shaped resistance switching layer has a horizontal portion and a vertical portion, and is formed on the bottom electrode layer. The oxygen ion diffusion barrier layers are formed on the inner and outer sidewalls of the vertical portion of the L-shaped resistance switching layers. The L-shaped resistance switching layers are between the top electrode layer and the bottom electrode layer.

Abstract: A method of fabricating a resistive random access memory cell includes the following steps. A second sacrificial layer is formed around a patterned stacked layer. An opening passing through first conductive layers and first sacrificial layers of the patterned stacked layer is formed. A second conductive layer is formed in the opening, and the second conductive layer and the first conductive layers form a first electrode layer. The first sacrificial layers and the second sacrificial layer are removed. A variable resistance layer and an oxygen reservoir layer are formed. The oxygen reservoir layer is patterned to form a patterned oxygen reservoir layer and expose the variable resistance layer. A second dielectric layer is formed on the variable resistance layer and the patterned oxygen reservoir layer. A second electrode is formed in the second dielectric layer.

Abstract: A resistive memory apparatus including bit lines, word lines, a memory array, bypass paths, select circuits, and a switch circuit is provided. The word lines are respectively crossed with the bit lines. The memory array includes memory elements. One end of each of the memory elements is coupled to the corresponding word line, and another end of each of the memory elements is coupled between a first node and a second node on the corresponding bit line. Each of the bypass paths is connected in parallel with the corresponding bit line between the first node point and the second node. Each of the select circuits is coupled to the corresponding bit line and bypass path, and configured to select the coupled bit line or bypass path. The switch circuit is coupled to the word lines, and configured to select one of the word lines.

Abstract: A resistive random access memory cell includes a first electrode layer, an oxygen reservoir layer, a variable resistance layer, and a second electrode. The first electrode layer is located on a dielectric layer, and includes a body part extending in a first direction and multiple extension parts connected to a sidewall of the body part and extending in a second direction. The second direction is perpendicular to the first direction. The oxygen reservoir layer covers the first electrode layer. The variable resistance layer is located between the first electrode layer and the oxygen reservoir layer. The second electrode is located above a top surface of the oxygen reservoir layer and around an upper sidewall of the oxygen reservoir layer.

Abstract: A resistive random access memory, including a first electrode layer and a second electrode layer disposed opposite to each other, a variable resistance layer located between the first electrode layer and the second electrode layer, an oxygen exchange layer located between the variable resistance layer and the second electrode layer, a vacancy-supplying layer surrounding a middle sidewall of the oxygen exchange layer; and a vacancy-driving electrode layer located on the vacancy-supply layer and surrounding an upper sidewall of the oxygen exchange layer, is provided. A method of fabricating the resistive random access memory is also provided.

Abstract: A resistive memory including a substrate, a first electrode, a second electrode, a resistance changeable layer and an oxygen reservoir layer is provided. The first electrode is located on the substrate. The second electrode is located between the first electrode and the substrate. The resistance changeable layer is located between the first electrode and the second electrode. The oxygen reservoir layer is located between the first electrode and the resistance changeable layer. The oxygen reservoir layer includes a first portion, a second portion and a third portion. The second portion is connected to one side of the first portion. The third portion is connected to the other side of the first portion. A thickness of the first portion is greater than a thickness of the second portion and a thickness of the third portion. The first portion of the oxygen reservoir layer protrudes toward the first electrode.

Abstract: A semiconductor structure includes a substrate, a first electrode, a vacancy supply layer, a sidewall barrier layer, an oxygen reservoir layer, a resistive switching layer, and a second electrode. The first electrode is disposed on the substrate. The vacancy supply layer is disposed on the first electrode. The sidewall barrier layer is disposed on the first electrode. The oxygen reservoir layer is disposed on the first electrode. The sidewall barrier layer is disposed between the oxygen reservoir layer and the vacancy supply layer. The resistive switching layer is disposed on the vacancy supply layer. The second electrode is disposed on the resistive switching layer.

Abstract: Provided is a resistive random access memory (RRAM) including a first electrode layer and a second electrode layer disposed opposite to each other, a variable resistance layer located between the first electrode layer and the second electrode layer, an oxygen exchange layer located between the variable resistance layer and the second electrode layer, a conductive layer laterally surrounding a sidewall of the oxygen exchange layer, a first barrier layer located between the conductive layer and the oxygen exchange layer and between the oxygen exchange layer and the variable resistance layer, and a second barrier layer located between the conductive layer and the second electrode layer and between the second electrode layer and the oxygen exchange layer.

Abstract: Provided is a method of manufacturing a resistive random access memory (RRAM) including: forming a lower electrode protruding from a top surface of a dielectric layer; conformally forming a data storage layer on the lower electrode and the dielectric layer; forming an oxygen reservoir material layer on the data storage layer; forming an opening in the oxygen reservoir material layer to expose the data storage layer on the lower electrode; forming an isolation structure in the opening, wherein the isolation structure divides the oxygen reservoir material layer into a first oxygen reservoir layer and a second oxygen reservoir layer; and forming an upper electrode on the first and second oxygen reservoir layers, wherein the first and second oxygen reservoir layers share the upper electrode.

Abstract: A resistive memory apparatus including bit lines, word lines, a memory array, bypass paths, select circuits, and a switch circuit is provided. The word lines are respectively crossed with the bit lines. The memory array includes memory elements. One end of each of the memory elements is coupled to the corresponding word line, and another end of each of the memory elements is coupled between a first node and a second node on the corresponding bit line. Each of the bypass paths is connected in parallel with the corresponding bit line between the first node point and the second node. Each of the select circuits is coupled to the corresponding bit line and bypass path, and configured to select the coupled bit line or bypass path. The switch circuit is coupled to the word lines, and configured to select one of the word lines.

Abstract: A RRAM and its manufacturing method are provided. The RRAM includes an interlayer dielectric layer, a first bottom contact structure, and a second bottom contact structure formed on a substrate. A first memory cell is formed on the first bottom contact structure. The first memory cell includes a first bottom electrode layer which includes a first conductive region. A pattern in which the first conductive region is vertically projected on the first bottom contact structure is a first projection pattern. A second memory cell is formed on the second bottom contact structure. The second memory cell includes a second bottom electrode layer which includes a second conductive region. A pattern in which the second conductive region is vertically projected on the second bottom contact structure is a second projection pattern. The second projection pattern is different from the first projection pattern.

Abstract: A conductive bridge random access memory and its manufacturing method are provided. The conductive bridge random access memory includes a bottom electrode, an inter-metal dielectric, a resistance switching assembly, and a top electrode. The bottom electrode is disposed on a substrate, and the inter-metal dielectric is disposed above the bottom electrode. The resistance switching assembly is disposed on the bottom electrode and positioned in the inter-metal dielectric. The resistance switching assembly has a reverse T-shape cross-section. The top electrode is disposed on the resistance switching assembly and the inter-metal dielectric.

Abstract: A method of forming the semiconductor device is provided. The method includes following steps. A memory structure is formed over a first conductive line over a substrate and is electrically connected to the first conductive line. A sacrificial layer is formed on the memory structure. A spacer layer is formed to cover the memory structure and the sacrificial layer. A first dielectric layer is formed to cover the spacer layer. A planarization process is performed to remove a portion of the first dielectric layer. A second dielectric layer is formed on the spacer layer and the first dielectric layer. A patterning process is performed to form an opening exposing a portion of the top surface of the sacrificial layer. The sacrificial layer is removed to form a recess. A second conductive line is formed in the opening and the recess to be electrically coupled to the memory structure.

Abstract: Provided are a resistive random access memory and a method of manufacturing the same. The resistive random access memory includes a stacked structure and a bit line structure. The stacked structure is disposed on a substrate. The stacked structure includes a bottom electrode, a top electrode and a resistance-switching layer. The bottom electrode is disposed on the substrate. The top electrode is disposed on the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The bit line structure covers a top surface of the stacked structure and covers a portion of a sidewall of the stacked structure. The bit line structure is electrically connected to the stacked structure.

Abstract: A resistive random access memory cell includes a first electrode layer, an oxygen reservoir layer, a variable resistance layer, and a second electrode. The first electrode layer is located on a dielectric layer, and includes a body part extending in a first direction and multiple extension parts connected to a sidewall of the body part and extending in a second direction. The second direction is perpendicular to the first direction. The oxygen reservoir layer covers the first electrode layer. The variable resistance layer is located between the first electrode layer and the oxygen reservoir layer. The second electrode is located above a top surface of the oxygen reservoir layer and around an upper sidewall of the oxygen reservoir layer.

Abstract: A semiconductor device and method of forming the same are provided. The semiconductor device includes a first conductive line over a substrate and a memory structure over the first conductive line. The memory structure is electrically coupled to the first conductive line through a conductive via. A spacer layer is laterally aside the memory structure and covers sidewalls of the memory structure. A first dielectric layer is on the spacer layer and laterally aside the memory structure. A second dielectric layer is on the memory structure, the spacer layer and the first dielectric layer. A second conductive line penetrates through the second dielectric layer, the first dielectric layer and the spacer layer to electrically couple to the memory structure. The second conductive line includes a body part at least partially embedded in the second dielectric layer and an extension part underlying the body part and laterally protruding from a sidewall of the body part.