Patents by Inventor Po-Yi Huang
Po-Yi Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240177950Abstract: A lighting keyboard is provided with at least one keyswitch, a support plate and a backlight module. The keyswitch has a keycap and a switch under the keycap. The support plate connects beneath the keycap by a support mechanism. The backlight module has a lighting board configured underneath the support plate and corresponding to the keycap. The lighting board includes a board, a first reflective layer and a circuit layer. The circuit layer is disposed on the board and includes a concave-convex structure and circuit traces. The circuit traces electrically connects with a light emitting unit. The first reflective layer covers the concave-convex structure to form microstructure regions.Type: ApplicationFiled: February 2, 2024Publication date: May 30, 2024Inventors: Heng-Yi Huang, Hsin-Cheng Ho, Po-Yueh Chou
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Patent number: 11978410Abstract: A method of backlight control for a display panel is provided. The display panel is configured to display with a variable refresh rate in a plurality of frame periods each having a fixed period and a variable period. The method includes steps of: generating a first backlight control signal in the fixed period of a frame period; determining whether a liquid crystal (LC) transition time corresponding to the frame period ends before an end time of the variable period of the frame period; generating a second backlight control signal in the variable period of the frame period when the LC transition time ends before the end time of the variable period of the frame period; and generating a compensation backlight control signal in a next frame period according to a backlight duty cycle of the frame period.Type: GrantFiled: June 23, 2022Date of Patent: May 7, 2024Assignee: NOVATEK Microelectronics Corp.Inventors: Po-Hsiang Huang, Chung-Wen Wu, Jiun-Yi Lin, Wen-Chi Lin
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Publication number: 20240144868Abstract: The present disclosure provides a pixel circuit with pulse width compensation, and the pixel circuit includes a pulse width modulation circuit and a pulse amplitude modulation circuit, and the pulse amplitude modulation circuit is electrically connected to the pulse width modulation circuit. The pulse width modulation circuit includes a P-type pulse width compensation transistor and a first P-type control transistor, and the first P-type control transistor is electrically connected to the P-type pulse width compensation transistor. The pulse amplitude modulation circuit includes a second P-type control transistor, a first capacitor, a P-type driving transistor and a light-emitting element. The second P-type control transistor is electrically connected to the first P-type control transistor. The first capacitor is electrically connected to the second P-type control transistor.Type: ApplicationFiled: December 8, 2022Publication date: May 2, 2024Inventors: De-Fu CHEN, Po Lun CHEN, Chun-Ta CHEN, Ta-Jen HUANG, Po-Tsun LIU, Guang-Ting ZHENG, Ting-Yi YI
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Publication number: 20240135897Abstract: The present disclosure provides a scan driving circuit, which includes a pull-up output charging circuit, a pull-down discharge circuit, a pre-charge circuit, an anti-noise start-up circuit and an anti-noise pull-down discharge circuit. The pull-up output charging circuit is electrically connected to an output terminal, and the pull-down discharge circuit is electrically connected to the output terminal. The pre-charge circuit is electrically connected to the pull-up output charging circuit and the pull-down discharge circuit through a driving node. The anti-noise start-up circuit is electrically connected to the pre-charge circuit. The anti-noise pull-down discharge circuit is electrically connected to the anti-noise start-up circuit, and the anti-noise pull-down discharge circuit is electrically connected to the driving node.Type: ApplicationFiled: December 11, 2022Publication date: April 25, 2024Inventors: De-Fu CHEN, Po Lun CHEN, Chun-Ta CHEN, Ta-Jen HUANG, Po-Tsun LIU, Guang-Ting ZHENG, Ting-Yi YI
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Publication number: 20240136401Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material and a passivation layer is disposed on the second semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material. A silicide is arranged within the passivation layer and along tops of the first doped region and the second doped region.Type: ApplicationFiled: January 5, 2024Publication date: April 25, 2024Inventors: Yin-Kai Liao, Sin-Yi Jiang, Hsiang-Lin Chen, Yi-Shin Chu, Po-Chun Liu, Kuan-Chieh Huang, Jyh-Ming Hung, Jen-Cheng Liu
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Patent number: 11967591Abstract: A method of forming a semiconductor device includes forming a first interconnect structure over a carrier; forming a thermal dissipation block over the carrier; forming metal posts over the first interconnect structure; attaching a first integrated circuit die over the first interconnect structure and the thermal dissipation block; removing the carrier; attaching a semiconductor package to the first interconnect structure and the thermal dissipation block using first electrical connectors and thermal dissipation connectors; and forming external electrical connectors, the external electrical connectors being configured to transmit each external electrical connection into the semiconductor device, the thermal dissipation block being electrically isolated from each external electrical connection.Type: GrantFiled: August 6, 2021Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Hao Chen, Fong-Yuan Chang, Po-Hsiang Huang, Ching-Yi Lin, Jyh Chwen Frank Lee
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Patent number: 11961489Abstract: The present disclosure provides a scan driving circuit, which includes a pull-up output charging circuit, a pull-down discharge circuit, a pre-charge circuit, an anti-noise start-up circuit and an anti-noise pull-down discharge circuit. The pull-up output charging circuit is electrically connected to an output terminal, and the pull-down discharge circuit is electrically connected to the output terminal. The pre-charge circuit is electrically connected to the pull-up output charging circuit and the pull-down discharge circuit through a driving node. The anti-noise start-up circuit is electrically connected to the pre-charge circuit. The anti-noise pull-down discharge circuit is electrically connected to the anti-noise start-up circuit, and the anti-noise pull-down discharge circuit is electrically connected to the driving node.Type: GrantFiled: December 11, 2022Date of Patent: April 16, 2024Assignees: Interface Technology (ChengDu) Co., Ltd., Interface Optoelectronics (ShenZhen) Co., Ltd., General Interface Solution LimitedInventors: De-Fu Chen, Po Lun Chen, Chun-Ta Chen, Ta-Jen Huang, Po-Tsun Liu, Guang-Ting Zheng, Ting-Yi Yi
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Patent number: 11947150Abstract: A backlit-module-embedded illuminated keyswitch structure includes a baseplate, a mask film disposed below the baseplate and having a first coating configured to substantially reflect a light, a light guide sheet disposed at one side of the mask film and having a light source hole, a reflective layer disposed at one side of the light guide sheet opposite to the mask film and having an opening communicating with the light source hole, a top glue configured to connect the mask film and the light guide sheet around the light source hole, and a bottom glue configured to connect the light guide sheet and the reflective layer around the light source hole. The first coating covers the light source hole. In a stacked direction of the mask film, the light guide sheet, and the reflective layer, at least one of the top glue and the bottom glue overlaps the first coating.Type: GrantFiled: March 30, 2023Date of Patent: April 2, 2024Assignee: DARFON ELECTRONICS CORP.Inventors: Heng-Yi Huang, Hsin-Cheng Ho, Po-Yueh Chou
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Publication number: 20240096781Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.Type: ApplicationFiled: March 20, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Ti Lu, Hao-Yi Tsai, Chia-Hung Liu, Yu-Hsiang Hu, Hsiu-Jen Lin, Tzuan-Horng Liu, Chih-Hao Chang, Bo-Jiun Lin, Shih-Wei Chen, Hung-Chun Cho, Pei-Rong Ni, Hsin-Wei Huang, Zheng-Gang Tsai, Tai-You Liu, Po-Chang Shih, Yu-Ting Huang
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Publication number: 20240088307Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chih-Hao Chang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
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Patent number: 11929318Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.Type: GrantFiled: May 10, 2021Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
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Publication number: 20240081077Abstract: A transistor includes a first semiconductor layer, a second semiconductor layer, a semiconductor nanosheet, a gate electrode and source and drain electrodes. The semiconductor nanosheet is physically connected to the first semiconductor layer and the second semiconductor layer. The gate electrode wraps around the semiconductor nanosheet. The source and drain electrodes are disposed at opposite sides of the gate electrode. The first semiconductor layer surrounds the source electrode, the second semiconductor layer surrounds the drain electrode, and the semiconductor nanosheet is disposed between the source and drain electrodes.Type: ApplicationFiled: September 1, 2022Publication date: March 7, 2024Applicants: Taiwan Semiconductor Manufacturing Company, Ltd., National Yang Ming Chiao Tung UniversityInventors: Po-Tsun Liu, Meng-Han Lin, Zhen-Hao Li, Tsung-Che Chiang, Bo-Feng Young, Hsin-Yi Huang, Sai-Hooi Yeong, Yu-Ming Lin
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Patent number: 11917923Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.Type: GrantFiled: April 28, 2021Date of Patent: February 27, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Ching-Hua Hsu, Si-Han Tsai, Shun-Yu Huang, Chen-Yi Weng, Ju-Chun Fan, Che-Wei Chang, Yi-Yu Lin, Po-Kai Hsu, Jing-Yin Jhang, Ya-Jyuan Hung
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Patent number: 11767504Abstract: Disclosed herein are albumin compositions having defined fatty acid profiles and methods of using the same. The albumin compositions described herein are suitable for use in cell culture methods, protein stabilization methods, amongst others. The albumin compositions described herein may improve the viability of and/or promote the growth of cells (e.g., mammalian cells) when the cells are cultured in a medium containing the albumin compositions. The albumin compositions described herein may improve the stability of a biologic when the biologic is in the presence of the albumin compositions. Further provided herein are methods of formulating albumin compositions having defined fatty acid profiles as described herein.Type: GrantFiled: August 14, 2020Date of Patent: September 26, 2023Assignee: Albcura CorporationInventors: Po-Yi Huang, Meng-Tsung Hsu, Pei-Chin Chen, Yu-Feng Liang, Chen-Yu Hsieh, Jeffy Chern
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Patent number: 11746349Abstract: Methods and compositions of altering a eukaryotic cell are described including providing to the eukaryotic cell a guide DNA sequence complementary to a target nucleic acid sequence, providing to the eukaryotic cell an Ago enzyme or a nuclease null Ago protein that interacts with the guide DNA sequence for DNA-guided gene editing and regulation of the target nucleic acid sequence in a site specific manner.Type: GrantFiled: February 7, 2017Date of Patent: September 5, 2023Assignee: President and Fellows of Harvard CollegeInventors: George M. Church, Luhan Yang, Margo R. Monroe, Po-Yi Huang
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Patent number: 11685942Abstract: A method of making a polypeptide including one or more D-amino acids is provided. The method includes combining a ribosome with protein translation factors including (1) a template encoding the polypeptide, wherein the template encoding the polypeptide includes one or more codons which have been recoded to accept a tRNA attached to a D-amino acid, (2) a plurality of L-amino acids and a plurality of corresponding tRNAs, (3) a plurality of D-amino acids and their corresponding aminoacyl tRNA synthetase or a plurality of tRNAs ligated with a D-amino acid, and (4) elongation factor P in a concentration of 2 to 20 micromolar, wherein translation of the template encoding the polypeptide occurs to produce the polypeptide including one or more D-amino acids.Type: GrantFiled: March 3, 2017Date of Patent: June 27, 2023Assignee: President and Fellows of Harvard CollegeInventors: George M. Church, Po-Yi Huang
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Publication number: 20220048976Abstract: Disclosed herein are albumin compositions having defined fatty acid profiles and methods of using the same. The albumin compositions described herein are suitable for use in cell culture methods, protein stabilization methods, amongst others. The albumin compositions described herein may improve the viability of and/or promote the growth of cells (e.g., mammalian cells) when the cells are cultured in a medium containing the albumin compositions. The albumin compositions described herein may improve the stability of a biologic when the biologic is in the presence of the albumin compositions. Further provided herein are methods of formulating albumin compositions having defined fatty acid profiles as described herein.Type: ApplicationFiled: August 14, 2020Publication date: February 17, 2022Inventors: Po-Yi Huang, Meng-Tsung Hsu, Pei-Chin Chen, Yu-Feng Liang, Chen-Yu Hsieh, Jeffy Chern
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Publication number: 20210189388Abstract: Methods and compositions of altering a eukaryotic cell are described including providing to the eukaryotic cell a guide DNA sequence complementary to a target nucleic acid sequence, providing to the eukaryotic cell an Ago enzyme or a nuclease null Ago protein that interacts with the guide DNA sequence for DNA-guided gene editing and regulation of the target nucleic acid sequence in a site specific manner.Type: ApplicationFiled: February 7, 2017Publication date: June 24, 2021Applicants: President and Fellows of Harvard College, President and Fellows of Harvard CollegeInventors: George M. Church, Luhan Yang, Margo R. Monroe, Po-Yi Huang
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Publication number: 20200283817Abstract: A method of making a polypeptide including one or more D-amino acids is provided that includes the use of elongation factor P with translational machinery.Type: ApplicationFiled: March 3, 2017Publication date: September 10, 2020Inventors: George M. Church, Po-Yi Huang
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Patent number: D1023047Type: GrantFiled: September 14, 2023Date of Patent: April 16, 2024Assignee: AI BIOLECTRONIC HEALTHTECH CO. LIMITEDInventors: Yen-Yi Ho, Huei-Yun Gong, Yen-Yun Huang, Po-Hao Huang