Abstract: A silicon on insulator (SOI) device includes a wafer and a trap-rich layer. The wafer includes a top silicon layer disposed on a buried oxide layer. The trap-rich layer having nano-dots and an oxide layer are stacked on a high resistivity substrate sequentially, wherein the oxide layer is bonded with the buried oxide layer. Or, a silicon on insulator (SOI) device includes a wafer and a high resistivity substrate. The wafer includes a top silicon layer disposed on a buried oxide layer. The high resistivity substrate is bonded with the buried oxide layer, wherein a positive fixed charge layer is induced at a surface of the buried oxide layer contacting the high resistivity substrate, and a doped negative charge layer is right next to the positive fixed charge layer. The present invention also provides a method of forming said silicon on insulator (SOI) device.

Abstract: A semiconductor structure includes a substrate, an insulating layer disposed on the substrate, an active layer disposed on the insulating layer, a first semiconductor device formed in a first device region of the active layer, a charge trap structure through the active layer and surrounding the first device region, and a charge trap layer between the insulating layer and the substrate and extending laterally to underlie the first device region and the charge trap structure.

Abstract: A method of forming a semiconductor structure. A first sacrificial gate is formed on a substrate. A spacer is formed on a sidewall of the first sacrificial gate. In the substrate, adjacent to the first sacrificial gate, a source region and a drain region are formed. A channel region is formed between the source region and the drain region. The first sacrificial gate is removed, and a gate trench is formed on the channel region between the spacers. The substrate is etched via the gate trench, thereby forming a recessed trench between the source region and the drain region, and extending into the substrate. The recessed trench has a hexagonal cross-sectional profile. A stress inducing material layer is then formed in the recessed trench. A channel layer is epitaxially grown on the stress inducing material layer. A gate structure is formed on the channel layer.

Abstract: A semiconductor device includes a substrate, a first transistor and a second transistor disposed on the substrate, and a first contact structure. The first transistor includes first semiconductor channel layers stacked and separated from one another, and a first source/drain structure and a second source/drain structure disposed at two opposite sides of and connected with each first semiconductor channel layer. The second transistor includes second semiconductor channel layers disposed above the first semiconductor channel layers, stacked, and separated from one another, and a third source/drain structure and a fourth source/drain structure disposed at two opposite sides of and connected with each second semiconductor channel layer. The first contact structure penetrates through the third source/drain structure.

Abstract: A shock absorber apparatus is provided. The shock absorber apparatus includes an elastic device and at least one mounting device connected to the elastic device. Each mounting device includes two securing elements. Each securing element is configured to secure an opposing portion of a structure. Each mounting device can also include two sliders. Each slider can have at least two surfaces, which are interconnected by an inclined surface facing an opposing slider, and a ground surface. The inclined surface can be slidably connected to one of the at least two securing elements. Each slider can be arranged to move in response to an applied force. The ground surface is configured to slidably connect to an inner wall of a box.

Abstract: A resistive memory device includes a first stacked structure and a second stacked structure. The first stacked structure includes a first bottom electrode, a first top electrode disposed on the first bottom electrode, and a first variable resistance layer disposed between the first bottom electrode and the first top electrode in a vertical direction. The second stacked structure includes a second bottom electrode, a second top electrode disposed on the second bottom electrode, and a second variable resistance layer disposed between the second bottom electrode and the second top electrode in the vertical direction. A thickness of the first variable resistance layer is less than a thickness of the second variable resistance layer for increasing the number of switchable resistance states of the resistive memory device.

Abstract: A multi-bit resistive random access memory cell includes a plurality of bottom electrodes, a plurality of dielectric layers, a top electrode and a resistance layer. The bottom electrodes and the dielectric layers are interleaved layers, each of the bottom electrodes is sandwiched by the dielectric layers, and a through hole penetrates through the interleaved layers. The top electrode is disposed in the through hole. The resistance layer is disposed on a sidewall of the through hole and is between the top electrode and the interleaved layers, thereby the top electrode, the resistance layer and the bottom electrodes constituting a multi-bit resistive random access memory cell. The present invention also provides a method of forming the multi-bit resistive random access memory cell.

Abstract: A method for regulating a position of an object includes detecting a plurality of first alignment structures of the object under rotation of the object, wherein a plurality of second alignment structures of the object sequentially face a photosensitive element during the rotation of the object, and when the plurality of first alignment structures have reached a first predetermined state, stopping the rotation of the object and performing an image capturing procedure of the object. The image capturing procedure includes: capturing a test image of the object, wherein the test image includes an image block presenting the second alignment structure currently facing the photosensitive element; detecting the position of the image block in the test image; when the image block is located in the middle of the test image, capturing a detection image of the object.

Abstract: A multi-bit resistive random access memory cell includes a plurality of bottom electrodes, a plurality of dielectric layers, a top electrode and a resistance layer. The bottom electrodes and the dielectric layers are interleaved layers, each of the bottom electrodes is sandwiched by the dielectric layers, and a through hole penetrates through the interleaved layers. The top electrode is disposed in the through hole. The resistance layer is disposed on a sidewall of the through hole and is between the top electrode and the interleaved layers, thereby the top electrode, the resistance layer and the bottom electrodes constituting a multi-bit resistive random access memory cell. The present invention also provides a method of forming the multi-bit resistive random access memory cell.

Abstract: A high electron mobility transistor, including an active area, a buffer layer on the active area, a channel layer on the buffer layer, a barrier layer on the channel layer, and gate, source and drain on the barrier layer, and a trench isolation structure adjacent and surrounding the channel layer and the barrier layer to apply stress and modify two-dimension hole gas (2DHG) of the high electron mobility transistor.

Abstract: A method of fabricating high electron mobility transistor, including the steps of providing a substrate with active areas, forming a buffer layer, a channel layer and a barrier layer sequentially on the substrate and gate, source and drain on the barrier layer, forming a trench surrounding the channel layer and the barrier layer, and forming a trench isolation structure in the trench, wherein the trench isolation structure applies stress on the channel layer and the barrier layer and modify two-dimension electron gas (2DEG) or two-dimension hole gas (2DHG) of the high electron mobility transistor.

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a patterned mask on the first barrier layer; forming a second barrier layer adjacent to two sides of the patterned mask; removing the patterned mask to form a recess; forming a gate electrode in the recess; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.

Abstract: A nanowire transistor structure includes a substrate. A first nanowire is suspended on the substrate. A first gate line crosses and surrounds the first nanowire. The first gate line includes a first end and a second end. A second gate line crosses and surrounds the first nanowire. The second gate line includes a third end and a fourth end. An interlayer dielectric encapsulates the first end, the second end, the third end and the fourth end. A first distance between the first end and the first nanowire is smaller than a third distance between the third end and the first nanowire.

Abstract: A high electron mobility transistor, including an active area, a buffer layer on the active area, a channel layer on the buffer layer, a barrier layer on the channel layer, and gate, source and drain on the barrier layer, and a trench isolation structure adjacent and surrounding the channel layer and the barrier layer to apply stress and modify two-dimension electron gas (2DEG) or two-dimension hole gas (2DHG) of the high electron mobility transistor.

Abstract: A semiconductor structure is disclosed, including a substrate, an insulating layer on the substrate, a barrier layer on the insulating layer, a bonding dielectric layer on the barrier layer, and a bonding pad extending through the insulating layer, the barrier layer and the bonding dielectric layer. A top surface of the bonding pad exposed from the bonding dielectric layer for bonding to another bonding pad on another substrate. A liner on a bottom surface of the bonding pad directly contacts the substrate.

Abstract: A method of forming a semiconductor structure. A first sacrificial gate is formed on a substrate. A spacer is formed on a sidewall of the first sacrificial gate. In the substrate, adjacent to the first sacrificial gate, a source region and a drain region are formed. A channel region is formed between the source region and the drain region. The first sacrificial gate is removed, and a gate trench is formed on the channel region between the spacers. The substrate is etched via the gate trench, thereby forming a recessed trench between the source region and the drain region, and extending into the substrate. The recessed trench has a hexagonal cross-sectional profile. A stress inducing material layer is then formed in the recessed trench. A channel layer is epitaxially grown on the stress inducing material layer. A gate structure is formed on the channel layer.

Abstract: A semiconductor structure is disclosed, including a substrate, an insulating layer on the substrate, a barrier layer on the insulating layer, a bonding dielectric layer on the barrier layer, and a bonding pad extending through the insulating layer, the barrier layer and the bonding dielectric layer. A top surface of the bonding pad exposed from the bonding dielectric layer for bonding to another bonding pad on another substrate. A liner on a bottom surface of the bonding pad directly contacts the substrate.

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a patterned mask on the first barrier layer; forming a second barrier layer adjacent to two sides of the patterned mask; removing the patterned mask to form a recess; forming a gate electrode in the recess; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.

Abstract: A multi-bit resistive random access memory cell includes a plurality of bottom electrodes, a plurality of dielectric layers, a top electrode and a resistance layer. The bottom electrodes and the dielectric layers are interleaved layers, each of the bottom electrodes is sandwiched by the dielectric layers, and a through hole penetrates through the interleaved layers. The top electrode is disposed in the through hole. The resistance layer is disposed on a sidewall of the through hole and is between the top electrode and the interleaved layers, thereby the top electrode, the resistance layer and the bottom electrodes constituting a multi-bit resistive random access memory cell. The present invention also provides a method of forming the multi-bit resistive random access memory cell.

Abstract: A method of forming a semiconductor structure is disclosed. First, a substrate is provided, including an upper surface. A gate structure is disposed on the upper surface. A spacer is disposed on a sidewall of the gate structure. A first region is located in the substrate. A second region is located in the substrate. The first region and the second region are dry etched to form a first trench and a second trench, respectively. The second region is masked. The first region is then wet etched through the first trench to form a widened first trench. A stress-inducing layer is then formed in the widened first trench and in the second trench.